公开(公告)号：US10346130B2

公开(公告)日：2019-07-09

申请号：US15593574

申请日：2017-05-12

Applicant: ARM Limited

Inventor： David Raymond Lutz

IPC: G06F7/483 ,  G06F7/485 ,  G06F5/01

Abstract: A data processing apparatus includes difference circuitry that calculates a difference between exponents of a first floating-point operand and a second floating-point operand. Shift circuitry generates a fractional string by shifting fractional bits of a selected operand of the first floating-point operand and the second floating-point operand based on the difference. Logic circuitry generates an integer-bit string representing an integer-bit of the selected operand having been shifted based on the difference. Combining circuitry combines the fractional string and the integer-bit string to produce a significand string representing the selected operand having been shifted based on the difference. The logic circuitry generates the integer-bit string using operations other than shifting.

公开(公告)号：US10331406B2

公开(公告)日：2019-06-25

申请号：US15816076

申请日：2017-11-17

Applicant: Arm Limited

Inventor： David Raymond Lutz ,  Thomas Gilles Tarridec

IPC: G06F7/499 ,  G06F7/483

Abstract: A data processing apparatus and method of operating a data processing apparatus are disclosed. Comparisons are made between first and second floating-point operands received. A more significant portion of the first floating-point operand and of the second floating-point operand are subject to comparison. The more significant portion of the first floating-point operand minus a least significant bit in the more significant portion is subject to comparison with the more significant portion of the second floating-point operand. A less significant portion of the first floating-point operand and of the second floating-point operand are also subject to comparison. In dependence on the outcome of these comparisons, right-shift circuitry is used selectively to perform a 1-bit right shift on a difference calculated between the first floating-point operand and the second floating-point operand.

公开(公告)号：US10275218B1

公开(公告)日：2019-04-30

申请号：US15793063

申请日：2017-10-25

Applicant: ARM LIMITED

Inventor： David Raymond Lutz

IPC: G06F7/483 ,  G06F7/485 ,  G06F7/499 ,  G06F7/544

Abstract: An apparatus and method are provided for subtracting a first significand value of a first floating-point operand and a second significand value of a second floating-point operand. Significand shift control circuitry asserts a shift signal when a difference is detected between at least one corresponding low order bit in the exponent values of the two floating-point operands. First processing circuitry is arranged to produce a first difference value by performing a first subtraction operation to subtract the second significand value from the first significand value when the shift signal is unasserted, and to subtract a right-shifted version of the second significand value from the first significand value when the shift signal is asserted. Second processing circuitry is arranged to produce a second difference value by performing a second subtraction operation to subtract the first significand value from the second significand value when the shift signal is unasserted, and to subtract a right-shifted version of the first significand value from the second significand value when the shift signal is asserted. First shift estimation circuitry is arranged to determine, from the significand values subjected to the first subtraction operation, a first estimated left shift amount, and similarly second shift estimation circuitry is arranged to determine, from the significand values subjected to the second subtraction operation, a second estimated left shift amount. Shifted difference value generation circuitry then produces, as a shifted difference value, the first difference value left shifted by the first estimated left shift amount when the first difference value is non-negative, and the second difference value left shifted by the second estimated left shift amount when the second difference value is non-negative. Such an approach can significantly reduce the time taken to generate a normalized difference value.

公开(公告)号：US10061561B2

公开(公告)日：2018-08-28

申请号：US15258051

申请日：2016-09-07

Applicant: ARM Limited

Inventor： David Raymond Lutz

IPC: G06F7/485 ,  G06F5/01

CPC classification number: G06F7/485 ,  G06F5/01 ,  G06F2205/00 ,  G06F2207/483

Abstract: A floating point adder includes leading zero anticipation circuitry to determine a number of leading zeros within a result significand value of a sum of a first floating point operand and a second floating point operand. This number of leading zeros is used to generate a mask which in turn selects input bits from a non-normalized significand produced by adding the first significand value and the second significand value. The non-normalized significand is then normalized at the same time as the output rounding bits used to round the normalized significand value are generated by rounding bit generation circuitry.

公开(公告)号：US09836279B2

公开(公告)日：2017-12-05

申请号：US14865359

申请日：2015-09-25

Applicant: ARM LIMITED

Inventor： David Raymond Lutz

IPC: G06F7/44 ,  G06F7/487 ,  G06F5/01

CPC classification number: G06F7/4876 ,  G06F5/012

Abstract: An apparatus and method for floating-point multiplication are provided. Two partial products are generated from two operand significands, which are then added to generate a product significand. The value of an unbiased result exponent is determined from the operand exponent values and leading zero counts, and a shift amount and direction for the product significand are determined in dependence on a predetermined minimum exponent value of a predetermined canonical format. The product significand is shifted by the shift amount in the shift direction. An overflow mask identifying an overflow bit position of the product significand is generated by right shifting a predetermined mask pattern by the shift amount, and the overflow mask is applied to the product significand to extract an overflow value at the overflow bit position. This extraction of the overflow value happens before the shift circuitry shifts the product significand, allowing an overall faster floating-point multiplication to be performed.

公开(公告)号：US09817661B2

公开(公告)日：2017-11-14

申请号：US14877003

申请日：2015-10-07

Applicant: ARM LIMITED

Inventor： David Raymond Lutz ,  Christopher Neal Hinds ,  Neil Burgess

IPC: G06F7/38 ,  G06F9/30 ,  G06F7/483

CPC classification number: G06F9/3001 ,  G06F7/483 ,  G06F7/49947 ,  G06F9/30 ,  G06F9/3016

Abstract: A data processing system supports execution of program instructions having a rounding position input operand so as to generate control signals for controlling processing circuitry to process a floating point input operand with a significand value to generate an output result which depends upon a value from rounding the floating point input operand using a variable rounding point within the significand of the floating point input operand as specified by the rounding position input operand. In this way, processing operations having as inputs floating point operands and anchored number operands may be facilitated.

公开(公告)号：US09678716B2

公开(公告)日：2017-06-13

申请号：US14579435

申请日：2014-12-22

Applicant: ARM Limited

Inventor： Neil Burgess ,  David Raymond Lutz

IPC: G06F7/544 ,  G06F7/509

CPC classification number: G06F7/509 ,  G06F7/544 ,  G06F2207/5442

Abstract: An apparatus comprises processing circuitry for performing an absolute difference operation for generating an absolute difference value in response to the first operand the second operand. The processing circuitry supports variable data element sizes for data elements of the first and second operands and the absolute difference value. Each data element of the absolute difference value represents an absolute difference between corresponding data elements of the first and second operands. The processing circuitry has an adding stage for performing at least one addition to generate at least one intermediate value and an inverting stage for inverting selected bits of each intermediate value. Control circuitry generates control information based on the current data element size and status information generated in the adding stage, to identify the selected bits to be inverted in the inverting stage to convert each intermediate value into a corresponding portion of the absolute difference value.

公开(公告)号：US09665347B2

公开(公告)日：2017-05-30

申请号：US14582812

申请日：2014-12-24

Applicant: ARM Limited

Inventor： David Raymond Lutz ,  Neil Burgess ,  Christopher Neal Hinds

IPC: G06F5/00 ,  G06F7/483 ,  G06F7/499 ,  G06F9/30 ,  G06F17/16 ,  H03M7/12 ,  H03M7/24 ,  G06F11/34 ,  G06F11/36 ,  G06F5/01 ,  G06F7/38 ,  G06F7/48 ,  G06F7/507 ,  G06F9/38 ,  G06F7/506

CPC classification number: G06F7/483 ,  G06F5/012 ,  G06F7/38 ,  G06F7/48 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/49921 ,  G06F7/49942 ,  G06F7/506 ,  G06F7/507 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/3885 ,  G06F11/3404 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/3636 ,  G06F11/3644 ,  G06F11/3648 ,  G06F17/16 ,  G06F2201/865 ,  G06F2207/483 ,  H03M7/12 ,  H03M7/24

Abstract: An apparatus comprises processing circuitry to perform a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a scalar value comprising an alternative representation of said binary value.

公开(公告)号：US09519456B2

公开(公告)日：2016-12-13

申请号：US14210609

申请日：2014-03-14

Applicant: ARM LIMITED

Inventor： David Raymond Lutz ,  Neil Burgess

IPC: G06F5/01 ,  G06F7/74

CPC classification number: G06F5/01 ,  G06F5/012 ,  G06F7/74

Abstract: A data processing apparatus and method are provided for performing a shift function on a binary number. The apparatus comprises count determination circuitry for determining a number of contiguous bit positions in the binary number that have a predetermined bit value, the count determination circuitry outputting a count value indicative of the number of contiguous bit positions determined. In parallel with the operation of the count determination circuitry, coarse shifting circuitry is used to determine, for at least one predetermined number of contiguous bit positions, whether that predetermined number of contiguous bit positions within the binary number has said predetermined bit value. An initial shift operation is then performed on the binary number based on that determination in order to produce an intermediate binary number. Once the count value is available from the count determination circuitry, fine shifting circuitry then performs a further shift operation on the intermediate binary number, based on the count value output by the count determination circuitry, in order to produce the result binary number. This provides an efficient mechanism for performing a shift function on a binary number, while still capturing the count value from the count determination circuitry.

Abstract translation: 提供了一种用于对二进制数执行移位功能的数据处理装置和方法。 该装置包括用于确定具有预定比特值的二进制数中的连续比特位数的计数确定电路，计数确定电路输出指示所确定的连续比特位数的计数值。 与计数确定电路的操作并行，粗移位电路用于对于至少一个预定数量的连续位位置来确定二进制数中的预定数量的连续位位置是否具有所述预定位值。 然后基于该确定对二进制数执行初始移位操作，以便产生中间二进制数。 一旦从计数确定电路获得计数值，微移位电路然后基于计数确定电路输出的计数值对中间二进制数执行进一步的移位操作，以便产生结果二进制数。 这提供了一种用于在二进制数字上执行移位功能的有效机制，同时仍然从计数确定电路捕获计数值。

公开(公告)号：US20160092168A1

公开(公告)日：2016-03-31

申请号：US14498118

申请日：2014-09-26

Applicant: ARM Limited

Inventor： David Raymond Lutz ,  Neil Burgess

IPC: G06F7/485 ,  G06F5/00

CPC classification number: H03M7/24

Abstract: A data processing apparatus has floating-point add circuitry to perform a floating-point addition operation for adding or subtracting two floating-point values. The apparatus also has conversion circuitry to perform a conversion operation to convert a first floating-point value into a second value having a different format. The conversion circuitry is capable of converting to an integer or fixed-point value. The conversion circuitry is physically distinct from the floating-point add circuitry.

Abstract translation: 数据处理装置具有浮点加法电路，用于执行用于相加或减去两个浮点值的浮点加法运算。 该装置还具有转换电路，用于执行转换操作以将第一浮点值转换为具有不同格式的第二值。 转换电路能够转换为整数或定点值。 转换电路在物理上不同于浮点加法电路。