公开(公告)号：US20200251152A1

公开(公告)日：2020-08-06

申请号：US16833154

申请日：2020-03-27

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Shidhartha Das ,  George McNeil Lattimore ,  Brian Tracy Cline

IPC: G11C5/06 ,  G11C14/00 ,  G11C8/10

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

公开(公告)号：US20200044644A1

公开(公告)日：2020-02-06

申请号：US16600366

申请日：2019-10-11

Applicant: Arm Limited

Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Robert Campbell Aitken

IPC: H03K17/14 ,  G11C13/00 ,  G11C29/02 ,  H01L45/00 ,  H01L49/00

Abstract: Subject matter disclosed herein may relate to programmable current for correlated electron switches.

公开(公告)号：US10049709B2

公开(公告)日：2018-08-14

申请号：US14986215

申请日：2015-12-31

Applicant: ARM Limited

Inventor： Gus Yeung ,  Fakhruddin Ali Bohra ,  George McNeil Lattimore

IPC: G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  G11C11/413

Abstract: Various implementations described herein may refer to and may be directed to using port modes with memory. In one implementation, a memory device may include access control circuitry used to selectively activate one of a plurality of first word-lines based on first address signals from a first access port, and used to selectively activate one of a plurality of second word-lines based on assigned address signals. The access control circuitry may include address selection circuitry configured to select the assigned address signals based on a port mode signal, where the address selection circuitry selects the first address signals as the assigned address signals when the port mode signal indicates a single port mode, and where the address selection circuitry selects second address signals from a second access port as the assigned address signals when the port mode signal indicates a dual port mode.