公开(公告)号：US20220342671A1

公开(公告)日：2022-10-27

申请号：US17241365

申请日：2021-04-27

Applicant: Arm Limited

Inventor： Michael Brian SCHINZLER ,  Muhammad Umar FAROOQ ,  Yasuo ISHII

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/30

Abstract: Aspects of the present disclosure relate an apparatus comprising fetch circuitry and instruction storage circuitry. The fetch circuitry is to fetch instructions for execution by execution circuitry. The instruction storage circuitry is to store temporary copies of fetched instructions. The fetch circuitry is configured to preferentially fetch instructions from the instruction storage circuitry. The instruction storage circuitry is configured to, responsive to a storage condition being met, begin storing copies of consecutive fetched instructions, the storage condition indicating a utility of a current fetched instruction; and to, responsive to determining that a number of said stored consecutive instructions has reached a storage threshold, cease storing copies of subsequent fetched instructions.

公开(公告)号：US20220147459A1

公开(公告)日：2022-05-12

申请号：US17093792

申请日：2020-11-10

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Adrian MONTERO ,  Joseph Michael PUSDESRIS ,  Karthik SUNDARAM ,  Yasuo ISHII

IPC: G06F12/0862

Abstract: Data processing apparatuses and methods of processing data are disclosed. The operations comprise: storing copies of data items; and storing, in a producer pattern history table, a plurality of producer-consumer relationships, each defining an association between producer load indicator and a plurality of consumer load entries, each consumer load entry comprising a consumer load indicator and one or more usefulness metrics. Further steps comprise: initiating, in response to a data load from an address corresponding to the producer load indicator in the producer pattern history table and when at least one of the corresponding one or more usefulness meets a criterion, a producer prefetch of data to be prefetched for storing as a local copy; and issuing, when the data is returned, one or more consumer prefetches to return consumer data from a consumer address generated from the data returned by the producer prefetch and a consumer load indicator of a consumer load entry.

公开(公告)号：US20220100666A1

公开(公告)日：2022-03-31

申请号：US17036442

申请日：2020-09-29

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Chang Joo LEE ,  James David DUNDAS ,  Muhammed Umar FAROOQ

IPC: G06F12/0864 ,  G06F9/38 ,  G06F12/0891

Abstract: A data processing apparatus and a method are disclosed. The data processing apparatus comprising: a prediction cache to store a plurality of prediction entries, each defining an association between a prediction cache lookup address and a predicted behaviour; prediction circuitry to select a prediction entry based on a prediction cache lookup of the prediction cache based on a given prediction cache lookup address and to determine the predicted behaviour associated with the given prediction cache lookup address based on the selected prediction entry; and a candidate prediction buffer to store a plurality of candidate predictions each indicative of a candidate prediction entry to be selected for inclusion in a subsequent prediction cache lookup, wherein the candidate prediction entry is selected in response to a candidate prediction lookup based on a candidate lookup address different to a candidate prediction cache lookup address indicated as associated with a candidate predicted behaviour in the candidate prediction entry.

公开(公告)号：US20210271486A1

公开(公告)日：2021-09-02

申请号：US16806063

申请日：2020-03-02

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Joseph Michael PUSDESRIS ,  Muhammad Umar FAROOQ

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/50

Abstract: An apparatus has processing circuitry, and history storage circuitry to store local history records. Each local history record corresponds to a respective subset of instruction addresses and tracks a sequence of observed instruction behaviour observed for successive instances of instructions having addresses in that subset. Pointer storage circuitry to store a shared pointer shared between the local history records. The shared pointer indicates a common storage position reached in each local history record. Prediction circuitry determines predicted instruction behaviour for a given instruction address based on a selected portion of a selected local history record stored in the history storage circuitry. The prediction circuitry selects the selected local history record based on the given instruction address and selects the selected portion based on the shared pointer.

公开(公告)号：US20210232400A1

公开(公告)日：2021-07-29

申请号：US16775431

申请日：2020-01-29

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Houdhaifa BOUZGUARROU ,  Thibaut Elie LANOIS ,  Guillaume BOLBENES

IPC: G06F9/38 ,  G06F1/03

Abstract: A branch predictor provides a predicted branch instruction outcome for a current block of at least one instruction. The branch predictor comprises branch prediction tables to store branch prediction entries providing branch prediction information; lookup circuitry to perform, based on indexing information associated with the current block, a table lookup in a looked up subset of the branch prediction tables; and prediction generating circuitry to generate the predicted branch instruction outcome for the current block based on the branch prediction information in the branch prediction entries looked up in the looked up subset of branch prediction tables. The looked up subset of branch prediction tables is selected based on lookup filtering information obtained for the current block. Lookups to tables other than the looked up subset are suppressed.

公开(公告)号：US20210067335A1

公开(公告)日：2021-03-04

申请号：US16550598

申请日：2019-08-26

Applicant: Arm Limited

Inventor： Jaekyu LEE ,  Yasuo ISHII ,  Dam SUNWOO

IPC: H04L9/08

Abstract: A data processing apparatus is provided that includes storage circuitry. Communication circuitry responds to an access request comprising a requested index with an access response comprising requested data. Coding circuitry performs a coding operation using a current key to: translate the requested index to an encoded index of the storage circuitry at which the requested data is stored or to translate encoded data stored at the requested index of the storage circuitry to the requested data. The current key is based on an execution environment. Update circuitry performs an update, in response to the current key being changed, of: the encoded index of the storage circuitry at which the requested data is stored or the encoded data.

公开(公告)号：US20210064528A1

公开(公告)日：2021-03-04

申请号：US16550607

申请日：2019-08-26

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Matthew Andrew RAFACZ ,  Guillaume BOLBENES ,  Houdhaifa BOUZGUARROU ,  . ABHISHEK RAJA

IPC: G06F12/0808 ,  G06F12/1027

Abstract: A data processing apparatus is provided. Cache circuitry caches data, the data being indexed according to execution contexts of processing circuitry. Receive circuitry receives invalidation requests each referencing a specific execution context in the execution contexts. Invalidation circuitry invalidates at least some of the data in the cache circuitry and filter circuitry filters the invalidation requests based on at least one condition and, when the condition is met, causes the invalidation circuitry to invalidate the data in the cache circuitry.

公开(公告)号：US20210019150A1

公开(公告)日：2021-01-21

申请号：US16514124

申请日：2019-07-17

Applicant: Arm Limited

Inventor： Michael Brian SCHINZLER ,  Michael FILIPPO ,  Yasuo ISHII

IPC: G06F9/38 ,  G06F9/30

Abstract: Apparatuses for data processing and methods of data processing are provided. A data processing apparatus performs data processing operations in response to a sequence of instructions including performing speculative execution of at least some of the sequence of instructions. In response to a branch instruction the data processing apparatus predicts whether or not the branch is taken or not taken further speculative instruction execution is based on that prediction. A path speculation cost is calculated in dependence on a number of recently flushed instructions and a rate at which speculatively executed instructions are issued may be modified based on the path speculation cost.

公开(公告)号：US20190166158A1

公开(公告)日：2019-05-30

申请号：US15825524

申请日：2017-11-29

Applicant: Arm Limited

Inventor： Thomas Christopher GROCUTT ,  Yasuo ISHII

IPC: H04L29/06

CPC classification number: H04L63/1441 ,  G06F9/3844 ,  G06F9/3861 ,  G06F21/53 ,  G06F21/78 ,  H04L63/1416

Abstract: A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.

公开(公告)号：US20240329999A1

公开(公告)日：2024-10-03

申请号：US18129979

申请日：2023-04-03

Applicant: Arm Limited

Inventor： Chang Joo LEE ,  Jason Lee SETTER ,  Julia Kay LANIER ,  Michael Brian SCHINZLER ,  Yasuo ISHII

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3861 ,  G06F9/3802

Abstract: An apparatus is provided for limiting the effective utilisation of an instruction fetch queue. The instruction fetch entries are used to control the prefetching of instructions from memory, such that those instructions are stored in an instruction cache prior to being required by execution circuitry while executing a program. By limiting the effective utilisation of the instruction fetch queue, fewer instructions will be prefetched and fewer instructions will be allocated to the instruction cache, thus causing fewer evictions from the instruction cache. In the event that the instruction fetch entries are for instructions that are unnecessary to the program, the pollution of the instruction cache with these unnecessary instructions can be mitigated.