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公开(公告)号:US20210258078A1
公开(公告)日:2021-08-19
申请号:US17175677
申请日:2021-02-14
Applicant: Ayar Labs, Inc.
Inventor: Roy Edward Meade , Vladimir Stojanovic , Chen Sun , Mark Wade , Hugo Saleh , Charles Wuischpard
IPC: H04B10/80 , H04B10/516
Abstract: A remote memory system includes a substrate of a multi-chip package, an integrated circuit chip connected to the substrate, and an electro-optical chip connected to the substrate. The integrated circuit chip includes a high-bandwidth memory interface. An electrical interface of the electro-optical chip is electrically connected to the high-bandwidth memory interface. A photonic interface of the electro-optical chip is configured to optically connect with an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals received through the electrical interface from the high-bandwidth interface into outgoing optical data signals. The optical macro transmits the outgoing optical data signals through the photonic interface to the optical link. The optical macro also converts incoming optical data signals received through the photonic interface into incoming electrical data signals. The optical macro transmits the incoming electrical data signals through the electrical interface to the high-bandwidth memory interface.
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公开(公告)号:US20210257288A1
公开(公告)日:2021-08-19
申请号:US17175490
申请日:2021-02-12
Applicant: Ayar Labs, Inc.
Inventor: Roy Edward Meade
IPC: H01L23/498 , G02B6/42 , H01L23/31 , H01L21/48 , H01L21/56
Abstract: A redistribution layer is formed on a carrier wafer. A cavity is formed within the redistribution layer. An electro-optical die is flip-chip connected to the redistribution layer. A plurality of optical fiber alignment structures within the electro-optical die is positioned over and exposed to the cavity. Mold compound material is disposed over the redistribution layer and the electro-optical die. A residual kerf region of the electro-optical die interfaces with the redistribution layer to prevent mold compound material from entering into the optical fiber alignment structures and the cavity. The carrier wafer is removed from the redistribution layer. The redistribution layer and the mold compound material are cut to obtain an electro-optical chip package that includes the electro-optical die. The cutting removes the residual kerf region from the electro-optical die to expose the plurality of optical fiber alignment structures and the cavity at an edge of the electro-optical chip package.
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公开(公告)号:US20200158950A1
公开(公告)日:2020-05-21
申请号:US16688904
申请日:2019-11-19
Applicant: Ayar Labs, Inc.
Inventor: Roy Edward Meade , Vladimir Stojanovic , Mark Wade
IPC: G02B6/12
Abstract: A photonic fanout die has a planar structure that has a top surface, a bottom surface, and outer side surfaces extending between the top surface and the bottom surface around an outer perimeter of the planar structure. The planar structure includes an opening formed within the outer perimeter. The opening has side surfaces that extend from the top surface to the bottom surface. The photonic fanout die also includes a plurality of optical waveguides formed within the planar structure to extend from a side surface of the opening to an outer side surface of the planar structure. The plurality of optical waveguides is configured such that a spacing between adjacent optical waveguides at the outer side surface of the planar structure is greater than a spacing between adjacent optical waveguides at the side surface of the opening.
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公开(公告)号:US20200021385A1
公开(公告)日:2020-01-16
申请号:US16510829
申请日:2019-07-12
Applicant: Ayar Labs, Inc.
Inventor: Vladimir Stojanovic , Alexandra Wright , Chen Sun , Mark Wade , Roy Edward Meade
Abstract: A TORminator module is disposed with a switch linecard of a rack. The TORminator module receives downlink electrical data signals from a rack switch. The TORminator module translates the downlink electrical data signals into downlink optical data signals. The TORminator module transmits multiple subsets of the downlink optical data signals through optical fibers to respective SmartDistributor modules disposed in respective racks. Each SmartDistributor module receives multiple downlink optical data signals through a single optical fiber from the TORminator module. The SmartDistributor module demultiplexes the multiple downlink optical data signals and distributes them to respective servers. The SmartDistributor module receives multiple uplink optical data signals from multiple servers and multiplexes them onto a single optical fiber for transmission to the TORminator module. The TORminator module coverts the multiple uplink optical data signals to multiple uplink electrical data signals, and transmits the multiple uplink electrical data signals to the rack switch.
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公开(公告)号:US20200021079A1
公开(公告)日:2020-01-16
申请号:US16513661
申请日:2019-07-16
Applicant: Ayar Labs, Inc.
Inventor: Roy Edward Meade
IPC: H01S5/02 , H01L25/075 , G02B6/43 , F21V8/00
Abstract: A wafer includes a number of die, with each die including electronic integrated circuits and optical devices. The wafer has a top surface and a bottom surface and a base layer. The bottom surface of the wafer corresponds to a bottom surface of the base layer. A wafer support system is attached to the top surface of the wafer. A thickness of the base layer is removed to expose a target layer within the wafer and to give the wafer a new bottom surface. A replacement handle structure is attached to the new bottom surface of the wafer. The replacement handle structure includes a first thickness region and a second thickness region. The first thickness region is positioned closest to the new bottom surface. The first thickness region is formed of an optical cladding material that mitigates optical coupling between optical devices within the die and the replacement handle structure.
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公开(公告)号:US20190271819A1
公开(公告)日:2019-09-05
申请号:US16287984
申请日:2019-02-27
Applicant: Ayar Labs, Inc.
Inventor: Roy Edward Meade , Vladimir Stojanovic
Abstract: A plurality of lid structures include at least one lid structure configured to overlie one or more heat sources within a multi-chip-module and at least one lid structure configured to overlie one or more temperature sensitive components within the multi-chip-module. The plurality of lid structures are configured and positioned such that each lid structure is separated from each adjacent lid structure by a corresponding thermal break. A heat spreader assembly is positioned in thermally conductive interface with the plurality of lid structures. The heat spreader assembly is configured to cover an aggregation of the plurality of lid structures. The heat spreader assembly includes a plurality of separately defined heat transfer members respectively configured and positioned to overlie the plurality of lid structures. The heat spreader assembly is configured to limit heat transfer between different heat transfer members within the heat spreader assembly.
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公开(公告)号:US20180019139A1
公开(公告)日:2018-01-18
申请号:US15646039
申请日:2017-07-10
Applicant: Ayar Labs, Inc.
Inventor: Chen Sun , Roy Edward Meade , Mark Wade , Alexandra Wright , Vladimir Stojanovic
CPC classification number: H01L21/6715 , B05D1/005 , G02B6/12004 , G02B6/1225 , G02B2006/12061 , G03F7/162 , G03F9/708 , G03F9/7084 , H01S5/0265
Abstract: A photoresist material is deposited, patterned, and developed on a backside of a wafer to expose specific regions on the backside of chips for etching. These specific regions are etched to form etched regions through the backside of the chips to a specified depth within the chips. The specified depth may correspond to an etch stop material. Etching of the backside of the wafer can also be done along the chip kerf regions to reduce stress during singulation/dicing of individual chips from the wafer. Etching of the backside of the chips can be done with the chips still part of the intact wafer. Or, the wafer having the pattered and developed photoresist on its backside can be singulated/diced before etching through the backside of the individual chips. The etched region(s) formed through the backside of a chip can be used for attachment of optical component(s) to the chip.
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公开(公告)号:US20240170387A1
公开(公告)日:2024-05-23
申请号:US18515078
申请日:2023-11-20
Applicant: Ayar Labs, Inc.
Inventor: Roy Edward Meade
IPC: H01L23/498 , G02B6/42 , H01L21/48 , H01L21/56 , H01L23/31
CPC classification number: H01L23/49838 , G02B6/4243 , H01L21/4857 , H01L21/561 , H01L21/563 , H01L21/568 , H01L23/3185 , H01L23/49822
Abstract: A redistribution layer is formed on a carrier wafer. A cavity is formed within the redistribution layer. An electro-optical die is flip-chip connected to the redistribution layer. A plurality of optical fiber alignment structures within the electro-optical die is positioned over and exposed to the cavity. Mold compound material is disposed over the redistribution layer and the electro-optical die. A residual kerf region of the electro-optical die interfaces with the redistribution layer to prevent mold compound material from entering into the optical fiber alignment structures and the cavity. The carrier wafer is removed from the redistribution layer. The redistribution layer and the mold compound material are cut to obtain an electro-optical chip package that includes the electro-optical die. The cutting removes the residual kerf region from the electro-optical die to expose the plurality of optical fiber alignment structures and the cavity at an edge of the electro-optical chip package.
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公开(公告)号:US11823990B2
公开(公告)日:2023-11-21
申请号:US17175490
申请日:2021-02-12
Applicant: Ayar Labs, Inc.
Inventor: Roy Edward Meade
IPC: G02B6/42 , H01L21/56 , H01L21/48 , H01L23/498 , H01L23/31
CPC classification number: H01L23/49838 , G02B6/4243 , H01L21/4857 , H01L21/561 , H01L21/563 , H01L21/568 , H01L23/3185 , H01L23/49822
Abstract: A redistribution layer is formed on a carrier wafer. A cavity is formed within the redistribution layer. An electro-optical die is flip-chip connected to the redistribution layer. A plurality of optical fiber alignment structures within the electro-optical die is positioned over and exposed to the cavity. Mold compound material is disposed over the redistribution layer and the electro-optical die. A residual kerf region of the electro-optical die interfaces with the redistribution layer to prevent mold compound material from entering into the optical fiber alignment structures and the cavity. The carrier wafer is removed from the redistribution layer. The redistribution layer and the mold compound material are cut to obtain an electro-optical chip package that includes the electro-optical die. The cutting removes the residual kerf region from the electro-optical die to expose the plurality of optical fiber alignment structures and the cavity at an edge of the electro-optical chip package.
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公开(公告)号:US11777633B2
公开(公告)日:2023-10-03
申请号:US17583185
申请日:2022-01-24
Applicant: Ayar Labs, Inc.
Inventor: Vladimir Stojanovic , Alexandra Wright , Chen Sun , Mark Wade , Roy Edward Meade
CPC classification number: H04J14/0209 , H04B10/5059 , H04J14/0267 , H04J14/0278 , H04Q11/0067 , H04Q11/0071 , G02B6/2938 , G02B6/4295 , G02B6/43
Abstract: A TORminator module is disposed with a switch linecard of a rack. The TORminator module receives downlink electrical data signals from a rack switch. The TORminator module translates the downlink electrical data signals into downlink optical data signals. The TORminator module transmits multiple subsets of the downlink optical data signals through optical fibers to respective SmartDistributor modules disposed in respective racks. Each SmartDistributor module receives multiple downlink optical data signals through a single optical fiber from the TORminator module. The SmartDistributor module demultiplexes the multiple downlink optical data signals and distributes them to respective servers. The SmartDistributor module receives multiple uplink optical data signals from multiple servers and multiplexes them onto a single optical fiber for transmission to the TORminator module. The TORminator module coverts the multiple uplink optical data signals to multiple uplink electrical data signals, and transmits the multiple uplink electrical data signals to the rack switch.
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