公开(公告)号：US20140211622A1

公开(公告)日：2014-07-31

申请号：US13752226

申请日：2013-01-28

申请人： Sailesh Kumar ,  Eric Norige ,  Joji Philip ,  Mahmud Hassan ,  Sundari Mitra ,  Joseph Rowlands

发明人： Sailesh Kumar ,  Eric Norige ,  Joji Philip ,  Mahmud Hassan ,  Sundari Mitra ,  Joseph Rowlands

IPC分类号： H04L12/56

CPC分类号： H04L47/125 ,  H04L45/66 ,  H04L47/70

摘要： Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem.

摘要翻译： 本文描述的系统和方法涉及基于网络片上（NoC）互连的解决方案，其基于系统业务流的带宽要求，自动且动态地确定NoC互连系统中所需的层数。 通过在映射不同NoC层的信道和路由之间的业务流的负载分担来动态分配和最小化层数。 可以分配附加层以提供可能需要用于死锁避免的附加虚拟通道并且维持各种系统流之间的隔离属性。 可以一起执行用于附加带宽和附加虚拟通道（VC）的层分配。

公开(公告)号：US08015359B1

公开(公告)日：2011-09-06

申请号：US11782238

申请日：2007-07-24

申请人： John Gregory Favor ,  Joseph Rowlands ,  Leonard Eric Shar ,  Richard Thaik

发明人： John Gregory Favor ,  Joseph Rowlands ,  Leonard Eric Shar ,  Richard Thaik

IPC分类号： G06F13/00

CPC分类号： G06F12/0815 ,  G06F9/3017 ,  G06F9/322 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3836 ,  G06F9/3844 ,  G06F12/0875 ,  G06F12/1027 ,  G06F12/1054 ,  Y02D10/13

摘要： An instruction processing circuit for a processor is disclosed. The instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution unit of the processor. The instruction processing circuit comprises at least one cache circuit and the processing circuit includes a sequencer and a page translation buffer coupled to the sequencer for trace verification and maintaining coherency between a memory and the at least one cache.

摘要翻译： 公开了一种用于处理器的指令处理电路。 指令处理电路适于基于一个或多个指令序列向处理器的执行单元提供一个或多个操作序列。 所述指令处理电路包括至少一个高速缓存电路，并且所述处理电路包括定序器和耦合到所述定序器的页面翻译缓冲器，用于跟踪验证并维持存储器与所述至少一个高速缓存之间的一致性。

公开(公告)号：US07941607B1

公开(公告)日：2011-05-10

申请号：US11782140

申请日：2007-07-24

申请人： Richard Thaik ,  John Gregory Favor ,  Joseph Rowlands ,  Leonard E. Shar ,  Matthew William Ashcraft

发明人： Richard Thaik ,  John Gregory Favor ,  Joseph Rowlands ,  Leonard E. Shar ,  Matthew William Ashcraft

IPC分类号： G06F13/00

CPC分类号： G06F12/0875 ,  G06F9/30174 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3836 ,  G06F12/1027 ,  G06F12/1054 ,  Y02D10/13

摘要： A method and system for promoting traces in an instruction processing circuit is disclosed. The method and system comprises determining if a current trace is promotable; and adding the current trace to a sequence buffer if the current trace is promotable. The current trace is marked as promoted and the current trace is marked as a first trace of a multi-block trace. The method and system includes determining if a next trace is promotable; adding the next trace to the sequence buffer if the next trace is promotable; and repeating the above until the next trace is not promotable and then adding the next trace to the sequence buffer if the next trace is not promotable.

摘要翻译： 公开了一种用于在指令处理电路中促进迹线的方法和系统。 所述方法和系统包括确定当前迹线是否可促进; 并且如果当前跟踪是可升级的，则将当前跟踪添加到序列缓冲器。 当前跟踪被标记为提升，当前跟踪被标记为多块跟踪的第一个跟踪。 所述方法和系统包括确定下一个跟踪是否可提升; 将下一个跟踪添加到序列缓冲区，如果下一个跟踪是可升级的; 并重复上述操作，直到下一个跟踪不可升级，然后如果下一个跟踪不可升级，则将下一个跟踪添加到序列缓冲区。

公开(公告)号：US20070282968A1

公开(公告)日：2007-12-06

申请号：US11891954

申请日：2007-08-14

申请人： Joseph Rowlands

发明人： Joseph Rowlands

IPC分类号： G06F15/167

CPC分类号： G06F13/4027 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F12/082 ,  G06F2212/2542

摘要： A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment, the interconnect does not permit retry of a transaction initiated thereon, and the memory bridge is configured to provide a response during a response phase of the transaction based on a state of a coherency block accessed by the transaction in the other nodes. In another embodiment, the node further comprises a plurality of interface circuits and a switch. Each of the plurality of interface circuits is configured to couple to an interface to receive coherency commands from other nodes. The switch is configured to selectively couple the plurality of interface circuits to the memory bridge to transmit the coherency commands to the memory bridge.

公开(公告)号：US20050172060A1

公开(公告)日：2005-08-04

申请号：US11069359

申请日：2005-03-01

申请人： Joseph Rowlands ,  David Anderson ,  Shailendra Desai

发明人： Joseph Rowlands ,  David Anderson ,  Shailendra Desai

IPC分类号： G06F13/00 ,  G06F13/14 ,  G06F13/16 ,  G06F13/368

CPC分类号： G06F13/1652 ,  G06F13/368

摘要： A distributed arbitration scheme includes arbiters with each agent. The arbiters receive request signals indicating which agents are arbitrating for the bus. Additionally, the agent currently using the bus broadcasts an agent identifier assigned to that agent. The arbiters receive the agent identifier and use the agent identifier as an indication of the winner of the preceding arbitration. Accordingly, the arbiters determine if the corresponding agent wins the arbitration, but may not attempt to calculate which other agent wins the arbitration. In one embodiment, the arbiter maintains a priority state indicative of which of the other agents are higher priority than the corresponding agent and which of the other agents are lower priority. In one implementation, the bus may be a split transaction bus and thus each requesting agent may include an address arbiter and each responding agent may include a data arbiter.

公开(公告)号：US20050038943A1

公开(公告)日：2005-02-17

申请号：US10950082

申请日：2004-09-24

申请人： James Cho ,  Joseph Rowlands ,  Mark Pearce

发明人： James Cho ,  Joseph Rowlands ,  Mark Pearce

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/423 ,  G06F13/4077

摘要： A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

摘要翻译： 系统包括总线和用于预充电总线的电路。 电路可以被耦合以接收与总线相关联的时钟信号，并且可以被配置为在时钟信号的周期的间隔期间对总线进行预充电，该间隔在第一边沿（上升沿或下降沿）之间以及随后的边沿 （下降或上升）。 该周期内的第二间隔并且不包括间隔可用于执行总线传送。 以这种方式，可以在相同的时钟周期中执行预充电和传输两者。 可以改善总线的带宽，因为可以在每个时钟周期发生传输，而不是具有用于预充电的非传输时钟周期。