公开(公告)号：US07688620B2

公开(公告)日：2010-03-30

申请号：US11834843

申请日：2007-08-07

申请人： Kwang-jin Lee ,  Choong-keun Kwak ,  Du-eung Kim

发明人： Kwang-jin Lee ,  Choong-keun Kwak ,  Du-eung Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0064

摘要： In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.

摘要翻译： 在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作 并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。

公开(公告)号：US06816429B2

公开(公告)日：2004-11-09

申请号：US10268380

申请日：2002-10-09

申请人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

发明人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

IPC分类号： G11C700

CPC分类号： G11C29/50

摘要： An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory device selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory device. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory devices.

摘要翻译： 提供了能够用AC应力进行老化测试的集成电路和使用其的测试方法。 集成电路包括地址转换装置和数据产生装置。 地址变换装置变换选择的存储器件的地址，并响应于时钟信号产生地址信号。 数据产生装置产生响应于时钟信号在第一状态和第二状态之间交替的数据信号，并将数据信号提供给选择的存储器件。 集成电路包括用于在测试期间将测试电源线连接到正常供电线的开关，并且响应于控制信号在正常操作期间从正常供电线截取测试电源线。 本发明的集成电路允许通过对所有的存储器件顺序并重复地施加AC应力来进行晶片老化测试。

公开(公告)号：US06490223B1

公开(公告)日：2002-12-03

申请号：US09614783

申请日：2000-07-12

申请人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

发明人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

IPC分类号： G11C800

CPC分类号： G11C29/50

摘要： An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory cell selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory cell. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory cells.

摘要翻译： 提供了能够用AC应力进行老化测试的集成电路和使用其的测试方法。 集成电路包括地址转换装置和数据产生装置。 地址变换装置对所选存储单元的地址进行变换，并根据时钟信号生成地址信号。 数据产生装置产生响应于时钟信号在第一状态和第二状态之间交替的数据信号，并将数据信号提供给选定的存储单元。 集成电路包括用于在测试期间将测试电源线连接到正常供电线的开关，并且响应于控制信号在正常操作期间从正常供电线截取测试电源线。 本发明的集成电路允许通过对所有的存储单元顺序并重复地施加AC应力来进行晶片老化测试。

公开(公告)号：US08179711B2

公开(公告)日：2012-05-15

申请号：US12273225

申请日：2008-11-18

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C5/02 ,  G11C7/18 ,  G11C11/15 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/24

摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。 每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。 每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

公开(公告)号：US07573766B2

公开(公告)日：2009-08-11

申请号：US11898125

申请日：2007-09-10

申请人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

发明人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

IPC分类号： G11C29/00

CPC分类号： G11C13/0004 ,  G11C29/50 ,  G11C2029/1204 ,  G11C2029/5006

摘要： Provided is a method of testing a phase change random access memory (PRAM). The method may include providing a plurality of PRAM cells each coupled between each of a plurality of first lines and each of a plurality of second lines intersecting the first lines, selecting at least one of the plurality of first lines while deselecting the remaining first lines and the plurality of second lines, pre-charging the selected at least one of the plurality of first lines to a predetermined or given voltage level, and sensing a change in the voltage level of the selected first line while supplying a monitoring voltage to the selected first line.

摘要翻译： 提供了一种测试相变随机存取存储器（PRAM）的方法。 该方法可以包括提供多个PRAM单元，每个PRAM单元分别耦合在多个第一线中的每一条与多条第一线相交的多条第二线中的每条之间，同时选择多条第一条线中的至少一条，同时取消选择其余的第一条线， 所述多个第二线路将所选择的所述多个第一线路中的至少一个预充电到预定或给定的电压电平，并且感测所选择的第一线路的电压电平的变化，同时向所选择的第一线路提供监视电压 线。

公开(公告)号：US07515459B2

公开(公告)日：2009-04-07

申请号：US11315129

申请日：2005-12-23

申请人： Sang-beom Kang ,  Du-eung Kim ,  Beak-hyung Cho ,  Hye-jin Kim

发明人： Sang-beom Kang ,  Du-eung Kim ,  Beak-hyung Cho ,  Hye-jin Kim

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A method of programming a memory array including a plurality of memory cells is provided. The memory cells may include phase-change memory elements. In one aspect, the method includes applying in succession first through nth current pulses to each of the memory cells to be programmed to a first state (e.g., a crystalline state), where a current amplitude of the first through nth current pulses decreases with each successive pulse, and where a pulse duration of the first through nth current pulses increases with each successive pulse.

摘要翻译： 提供了一种编程包括多个存储单元的存储器阵列的方法。 存储器单元可以包括相变存储元件。 在一个方面，该方法包括将第一至第n电流脉冲连续地应用于要被编程到第一状态（例如，结晶状态）的每个存储器单元，其中第一至第n电流脉冲的电流幅度随着每个 连续脉冲，并且其中第一至第n电流脉冲的脉冲持续时间随着每个连续脉冲而增加。

公开(公告)号：US07876609B2

公开(公告)日：2011-01-25

申请号：US12720918

申请日：2010-03-10

申请人： Kwang-jin Lee ,  Choong-keun Kwak ,  Du-eung Kim

发明人： Kwang-jin Lee ,  Choong-keun Kwak ,  Du-eung Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0064

摘要： In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.

摘要翻译： 在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作 并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。

公开(公告)号：US07453716B2

公开(公告)日：2008-11-18

申请号：US11238381

申请日：2005-09-29

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

摘要： In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了相变存储单元，每个都包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个相变存储单元组。 每个相变存储单元组的每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个相变存储单元的电流量。

公开(公告)号：US20080062741A1

公开(公告)日：2008-03-13

申请号：US11898125

申请日：2007-09-10

申请人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

发明人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

IPC分类号： G11C29/44

CPC分类号： G11C13/0004 ,  G11C29/50 ,  G11C2029/1204 ,  G11C2029/5006

摘要： Provided is a method of testing a phase change random access memory (PRAM). The method may include providing a plurality of PRAM cells each coupled between each of a plurality of first lines and each of a plurality of second lines intersecting the first lines, selecting at least one of the plurality of first lines while deselecting the remaining first lines and the plurality of second lines, pre-charging the selected at least one of the plurality of first lines to a predetermined or given voltage level, and sensing a change in the voltage level of the selected first line while supplying a monitoring voltage to the selected first line.

摘要翻译： 提供了一种测试相变随机存取存储器（PRAM）的方法。 该方法可以包括提供多个PRAM单元，每个PRAM单元分别耦合在多个第一线中的每一条与多条第一线相交的多条第二线中的每条之间，同时选择多条第一条线中的至少一条，同时取消选择其余的第一条线， 所述多个第二线路将所选择的所述多个第一线路中的至少一个预充电到预定或给定的电压电平，并且感测所选择的第一线路的电压电平的变化，同时向所选择的第一线路提供监视电压 线。

公开(公告)号：US20090168493A1

公开(公告)日：2009-07-02

申请号：US12273225

申请日：2008-11-18

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00 ,  H01L21/00 ,  H01L47/00

CPC分类号： G11C13/003 ,  G11C5/02 ,  G11C7/18 ,  G11C11/15 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/24

摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。 每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。 每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。