公开(公告)号：US07725660B2

公开(公告)日：2010-05-25

申请号：US11828448

申请日：2007-07-26

申请人： Gary Dale Carpenter ,  Scott Douglas Clark ,  Bernard Charles Drerup ,  Russell Dean Hoover ,  Charles Ray Johns ,  David John Krolak ,  Prasanna Srinivasan ,  Thuong Quang Truong

发明人： Gary Dale Carpenter ,  Scott Douglas Clark ,  Bernard Charles Drerup ,  Russell Dean Hoover ,  Charles Ray Johns ,  David John Krolak ,  Prasanna Srinivasan ,  Thuong Quang Truong

IPC分类号： G06F12/00

CPC分类号： G06F12/0822

摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system.

摘要翻译： 一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。 本地节点确定请求是本地还是系统请求。 如果请求是本地请求，则执行本地节点中的目录的查找。 如果本地节点目录中的条目指示请求中的数据不具有远程所有者，并且请求没有远程目标，则在本地节点上解析数据的一致性，并且传输 如果需要，请求中指定的数据将被执行，并且请求是本地请求。 如果条目指示数据具有远程所有者或请求具有远程目标，则将请求转发到多节点系统中的所有远程节点。

公开(公告)号：US20090132743A1

公开(公告)日：2009-05-21

申请号：US12353299

申请日：2009-01-14

申请人： Bernard Charles Drerup ,  Richard Siegmund, JR. ,  Barry Joe Wolford

发明人： Bernard Charles Drerup ,  Richard Siegmund, JR. ,  Barry Joe Wolford

IPC分类号： G06F13/40

CPC分类号： G06F13/4022

摘要： An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.

摘要翻译： 描述了一种用于计算机系统中的数据处理的装置。 该装置包括具有数据处理主机，功能耦合的数据处理器核心和功能耦合的数据处理器从机的数据处理设备。 数据处理主机和数据处理从机都耦合到公共总线或公共交叉开关。 数据处理设备处理与传送到数据处理器从站或从数据处理器从站传输相关联的数据。 系统主人将将需要数据处理的事务指向数据处理从站，这将与目标存储器从站间接交互。 系统主人将直接向目标内存从站直接进行不需要数据处理的事务。

公开(公告)号：US06985972B2

公开(公告)日：2006-01-10

申请号：US10264163

申请日：2002-10-03

申请人： James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Jaya Prakash Subramaniam Ganasan ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Thomas Philip Speier ,  Barry Joe Wolford

发明人： James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Jaya Prakash Subramaniam Ganasan ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Thomas Philip Speier ,  Barry Joe Wolford

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F13/366 ,  G06F12/0831 ,  G06F2212/1028 ,  G06F2213/0038 ,  Y02D10/13 ,  Y02D10/14

摘要： A data processing system with a snooper that is capable of dynamically enabling and disabling its snooping capabilities (i.e., snoop detect and response). The snooper is connected to a bus controller via a plurality of interconnects, including a snooperPresent signal, a snoop response signal and a snoop detect signal. When the snooperPresent signal is asserted, subsequent snoop requests are sent to the snooper, and the snooper is polled for a snoop response. Each snooper is capable of responding at different times (i.e., each snooper operates with different snoop latencies). The bus controller individually tracks the snoop response received from each snooper with the snooperPresent signal enabled. Whenever the snooper wishes to deactivate its snooping capabilities/operations, the snooper de-asserts the snooperPresent signal. The bus controller recognizes this as an indication that the snooper is unavailable. Thus, when the bus controller broadcasts subsequent snoop requests, the bus controller does not send the snoop request to the snooper.

摘要翻译： 具有能够动态地启用和禁用其窥探能力（即，窥探检测和响应）的窥探者的数据处理系统。 窥探者通过多个互连连接到总线控制器，包括窥探信号，窥探响应信号和窥探检测信号。 当snooperPresent信号被断言时，后续的窥探请求被发送到snooper，并且窥探者被轮询以进行侦听响应。 每个窥探者都能够在不同的时间进行响应（即，每个窥探者使用不同的侦听延迟进行操作）。 总线控制器单独跟踪snooperPresent信号启用时从每个窥探者接收的窥探响应。 只要窥探者希望取消其窥探能力/操作，窥探者将断言snooperPresent信号。 总线控制器将此识别为snooper不可用的指示。 因此，当总线控制器广播后续的窥探请求时，总线控制器不向窥探者发送窥探请求。

公开(公告)号：US06819726B2

公开(公告)日：2004-11-16

申请号：US09732000

申请日：2000-12-07

申请人： Bernard Charles Drerup ,  Richard Siegmund, Jr.

发明人： Bernard Charles Drerup ,  Richard Siegmund, Jr.

IPC分类号： H03K514

CPC分类号： H03L7/00 ,  H03L7/06

摘要： The invention includes a circuit for aligning the phase of a clock derived from a frequency multiplied version of a reference clock used in a computer system. The dynamic phase alignment circuit includes a few logic gates to perform the operation of delaying the derived clock, detecting its phase misalignment, and correcting such misalignment by incrementally aligning the phase of the derived clock to the reference clock. The invention is capable of aligning the phase of a derived clock to a reference clock in a computer system whose CPU operates at as high a frequency as about 500 MHz or higher.

摘要翻译： 本发明包括用于对准从在计算机系统中使用的参考时钟的倍增版本导出的时钟的相位的电路。 动态相位对准电路包括几个逻辑门，用于执行延迟导出时钟的操作，检测其相位未对准，以及通过将导出的时钟的相位逐渐对准到参考时钟来校正这种不对准。 本发明能够将得到的时钟的相位与计算机系统中的基准时钟对准，该计算机系统的CPU以高于约500MHz或更高的频率工作。

公开(公告)号：US5740364A

公开(公告)日：1998-04-14

申请号：US686851

申请日：1996-07-26

申请人： Bernard Charles Drerup

发明人： Bernard Charles Drerup

IPC分类号： G06F13/00 ,  G06F1/00 ,  G06F3/033 ,  G06F3/048 ,  G06F21/00 ,  H04L29/06 ,  H04L29/08

CPC分类号： G06F3/0481 ,  G06F21/6218 ,  G06F21/83 ,  G06Q20/105 ,  H04L29/06 ,  G06F2221/2153 ,  H04L67/06 ,  H04L67/10 ,  H04L69/329 ,  Y10S707/99931

摘要： A system and method are provided wherein a user of an interconnected computer system can identify a specific piece of data and then access this data from another computer in the network. This is extremely useful since it is often desirable for data to be capable of being displayed and manipulated from another system during meetings, discussions and the like. The user who wishes to transfer a file to another system simply points an untethered stylus to a representation of a file, such as a filename, icon, or the like and then selects the file to be transferred. The user then carries the stylus to a remote interconnected computer and points the stylus at the remote computer which verifies the identity of the stylus and obtains a path to the selected file. The data file is then transferred from the user's computer to the remote computer through the network.

摘要翻译： 提供了一种系统和方法，其中互连的计算机系统的用户可以识别特定的数据片段，然后从网络中的另一计算机访问该数据。 这是非常有用的，因为在会议，讨论等期间，通常希望能够从另一个系统显示和操纵数据。 希望将文件传送到另一个系统的用户只需将未连接的手写笔指向诸如文件名，图标等的文件的表示，然后选择要传送的文件。 然后，用户将触控笔携带到远程互连的计算机，并将触笔指向远程计算机，以验证触笔的身份，并获得到所选文件的路径。 然后通过网络将数据文件从用户计算机传输到远程计算机。

公开(公告)号：US08108618B2

公开(公告)日：2012-01-31

申请号：US11928547

申请日：2007-10-30

申请人： Bernard Charles Drerup

发明人： Bernard Charles Drerup

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0837

摘要： An information handling system includes a processor integrated circuit including multiple processors with respective processor cache memories. Enhanced cache coherency protocols achieve cache memory integrity in a multi-processor environment. A processor bus controller manages cache coherency bus interfaces to master devices and slave devices. In one embodiment, a master I/O device controller and a slave I/O device controller couple directly to the processor bus controller while system memory couples to the processor bus controller via a memory controller. In one embodiment, the processor bus controller blocks partial responses that it receives from all devices except the slave I/O device from being included in a combined response that the processor bus controller sends over the cache coherency buses.

摘要翻译： 信息处理系统包括处理器集成电路，其包括具有相应处理器高速缓冲存储器的多个处 增强的高速缓存一致性协议在多处理器环境中实现高速缓存存储器完整性。 处理器总线控制器管理高速缓存一致性总线接口到主设备和从设备。 在一个实施例中，主I / O设备控制器和从I / O设备控制器直接耦合到处理器总线控制器，同时系统存储器经由存储器控制器耦合到处理器总线控制器。 在一个实施例中，处理器总线控制器阻止从除了从I / O设备之外的所有设备接收的部分响应被包括在处理器总线控制器通过高速缓存一致性总线发送的组合响应中。

公开(公告)号：US07882278B2

公开(公告)日：2011-02-01

申请号：US12362585

申请日：2009-01-30

申请人： Sundeep Chadha ,  Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

发明人： Sundeep Chadha ,  Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

IPC分类号： G06F13/42

CPC分类号： G06F13/4059

摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.

摘要翻译： 用于数据总线通信的控制机制采用分配总线事务的通道，每个通道具有独立的流量控制。 控制机制强制通道之间的排序算法，由此至少一些交易可以通过其他交易。 通道属性可编程以改变排序条件。 优选地，每个信道被分配其自己的可编程缓冲区。 控制机制为每个通道独立地确定缓冲区空间是否可用，并相应地为每个通道独立地执行流量控制。 流量控制优选地是基于信用的，表示缓冲区空间的信用或接收器接收数据的一些其他容量。 优选地，流量控制机构包括控制集成电路芯片的内部通信的中央互连模块。

公开(公告)号：US20090138629A1

公开(公告)日：2009-05-28

申请号：US12362585

申请日：2009-01-30

申请人： Sundeep Chadha ,  Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

发明人： Sundeep Chadha ,  Mark Anthony Check ,  Bernard Charles Drerup ,  Michael Grassi

IPC分类号： G06F13/42

CPC分类号： G06F13/4059

摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.

摘要翻译： 用于数据总线通信的控制机制采用分配总线事务的通道，每个通道具有独立的流量控制。 控制机制强制通道之间的排序算法，由此至少一些交易可以通过其他交易。 通道属性可编程以改变排序条件。 优选地，每个信道被分配其自己的可编程缓冲区。 控制机制为每个通道独立地确定缓冲区空间是否可用，并相应地为每个通道独立地执行流量控制。 流量控制优选地是基于信用的，表示缓冲区空间的信用或接收器接收数据的一些其他容量。 优选地，流量控制机构包括控制集成电路芯片的内部通信的中央互连模块。

公开(公告)号：US20090113098A1

公开(公告)日：2009-04-30

申请号：US11928547

申请日：2007-10-30

申请人： Bernard Charles Drerup

发明人： Bernard Charles Drerup

IPC分类号： G06F13/18

CPC分类号： G06F12/0837

摘要： An information handling system includes a processor integrated circuit including multiple processors with respective processor cache memories. Enhanced cache coherency protocols achieve cache memory integrity in a multi-processor environment. A processor bus controller manages cache coherency bus interfaces to master devices and slave devices. In one embodiment, a master I/O device controller and a slave I/O device controller couple directly to the processor bus controller while system memory couples to the processor bus controller via a memory controller. In one embodiment, the processor bus controller blocks partial responses that it receives from all devices except the slave I/O device from being included in a combined response that the processor bus controller sends over the cache coherency buses.

摘要翻译： 信息处理系统包括处理器集成电路，其包括具有相应处理器高速缓冲存储器的多个处理器。 增强的高速缓存一致性协议在多处理器环境中实现高速缓存存储器完整性。 处理器总线控制器管理高速缓存一致性总线接口到主设备和从设备。 在一个实施例中，主I / O设备控制器和从I / O设备控制器直接耦合到处理器总线控制器，同时系统存储器经由存储器控制器耦合到处理器总线控制器。 在一个实施例中，处理器总线控制器阻止从除了从I / O设备之外的所有设备接收的部分响应被包括在处理器总线控制器通过高速缓存一致性总线发送的组合响应中。

公开(公告)号：US20090113097A1

公开(公告)日：2009-04-30

申请号：US11927911

申请日：2007-10-30

申请人： Bernard Charles Drerup ,  Richard Nicholas ,  Prasanna Srinivasan

发明人： Bernard Charles Drerup ,  Richard Nicholas ,  Prasanna Srinivasan

IPC分类号： G06F13/00

CPC分类号： G06F13/385

摘要： In a method and apparatus associated with a bus controller, a set of mechanisms are selectively added to the bus controller, as well as to slave devices connected to the bus controller. A mechanism is also added to one or more master devices connected to the bus controller, in order to provide the master devices with a transaction ordering capability. The added mechanisms collectively achieve the objective of supporting connection of multiple slave devices to a common controller interface, and at the same time allowing pipelined operation of the slave devices. One embodiment of the invention is directed to a method for use with a bus and an associated bus controller, wherein the bus controller has respective master and slave interfaces for use in selectively interconnecting master devices and slave devices. The method comprises the steps of connecting one or more of the master devices to one of the master interfaces, and connecting each of a plurality of slave devices to the same one of the slave interfaces. The method further comprises operating a connected master device to send multiple commands to a selected one of the connected slave devices in accordance with a command pipelining procedure.

摘要翻译： 在与总线控制器相关联的方法和装置中，一组机制被选择性地添加到总线控制器以及连接到总线控制器的从设备。 为了向主设备提供事务排序能力，还将一种机制添加到连接到总线控制器的一个或多个主设备中。 所附加的机制共同实现支持多个从设备连接到公共控制器接口的目的，并且同时允许从设备的流水线操作。 本发明的一个实施例涉及一种与总线和相关联的总线控制器一起使用的方法，其中总线控制器具有用于选择性地互连主设备和从设备的主和从接口。 该方法包括以下步骤：将一个或多个主设备连接到一个主接口，并将多个从设备中的每一个连接到同一个从接口。 该方法还包括操作连接的主设备，以根据命令流水线过程向连接的从设备中的所选一个发送多个命令。