公开(公告)号：US07669013B2

公开(公告)日：2010-02-23

申请号：US11828439

申请日：2007-07-26

申请人： Gary Dale Carpenter ,  Scott Douglas Clark ,  Bernard Charles Drerup ,  Russell Dean Hoover ,  Charles Ray Johns ,  David John Krolak ,  Prasanna Srinivasan ,  Thuong Quang Truong

发明人： Gary Dale Carpenter ,  Scott Douglas Clark ,  Bernard Charles Drerup ,  Russell Dean Hoover ,  Charles Ray Johns ,  David John Krolak ,  Prasanna Srinivasan ,  Thuong Quang Truong

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F12/0831

摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a system request. If a directory entry indicates that data specified in the request has a local owner or local destination, the request is forwarded to the local node. If the local node determines that the request is a local request, a look-up of the local node directory is performed. If the directory entry indicates that data specified in the request has a local owner and local destination, the coherency of the data on the local node is resolved and a transfer of the request data is performed if required. Otherwise, the request is forwarded to all remote nodes in the multi-node system.

摘要翻译： 一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。 如果在本地节点的多节点桥接处接收到的请求是系统请求，则执行本地节点目录的查找。 如果目录项指示请求中指定的数据具有本地所有者或本地目标，则请求将转发到本地节点。 如果本地节点确定请求是本地请求，则执行本地节点目录的查找。 如果目录条目指示请求中指定的数据具有本地所有者和本地目标，则解析本地节点上的数据的一致性，并且如果需要，则执行请求数据的传输。 否则，请求将转发到多节点系统中的所有远程节点。

公开(公告)号：US20090031086A1

公开(公告)日：2009-01-29

申请号：US11828448

申请日：2007-07-26

申请人： Gary Dale Carpenter ,  Scott Douglas Clark ,  Bernard Charles Drerup ,  Russell Dean Hoover ,  Charles Ray Johns ,  David John Krolak ,  Prasanna Srinivasan ,  Thuong Quang Truong

发明人： Gary Dale Carpenter ,  Scott Douglas Clark ,  Bernard Charles Drerup ,  Russell Dean Hoover ,  Charles Ray Johns ,  David John Krolak ,  Prasanna Srinivasan ,  Thuong Quang Truong

IPC分类号： G06F12/16

CPC分类号： G06F12/0822

摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system.

摘要翻译： 一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。 本地节点确定请求是本地还是系统请求。 如果请求是本地请求，则执行本地节点中的目录的查找。 如果本地节点目录中的条目指示请求中的数据不具有远程所有者，并且请求没有远程目标，则在本地节点上解析数据的一致性，并且传输 如果需要，请求中指定的数据将被执行，并且请求是本地请求。 如果条目指示数据具有远程所有者或请求具有远程目标，则将请求转发到多节点系统中的所有远程节点。

公开(公告)号：US20090031085A1

公开(公告)日：2009-01-29

申请号：US11828439

申请日：2007-07-26

申请人： Gary Dale Carpenter ,  Scott Douglas Clark ,  Bernard Charles Drerup ,  Russell Dean Hoover ,  Charles Ray Johns ,  David John Krolak ,  Prasanna Srinivasan ,  Thuong Quang Truong

发明人： Gary Dale Carpenter ,  Scott Douglas Clark ,  Bernard Charles Drerup ,  Russell Dean Hoover ,  Charles Ray Johns ,  David John Krolak ,  Prasanna Srinivasan ,  Thuong Quang Truong

IPC分类号： G06F12/16

CPC分类号： G06F12/0817 ,  G06F12/0831

摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a system request. If a directory entry indicates that data specified in the request has a local owner or local destination, the request is forwarded to the local node. If the local node determines that the request is a local request, a look-up of the local node directory is performed. If the directory entry indicates that data specified in the request has a local owner and local destination, the coherency of the data on the local node is resolved and a transfer of the request data is performed if required. Otherwise, the request is forwarded to all remote nodes in the multi-node system.

摘要翻译： 一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。 如果在本地节点的多节点桥接处接收到的请求是系统请求，则执行本地节点目录的查找。 如果目录项指示请求中指定的数据具有本地所有者或本地目标，则请求将转发到本地节点。 如果本地节点确定请求是本地请求，则执行本地节点目录的查找。 如果目录条目指示请求中指定的数据具有本地所有者和本地目标，则解析本地节点上的数据的一致性，并且如果需要，则执行请求数据的传输。 否则，请求将转发到多节点系统中的所有远程节点。

公开(公告)号：US07725660B2

公开(公告)日：2010-05-25

申请号：US11828448

申请日：2007-07-26

申请人： Gary Dale Carpenter ,  Scott Douglas Clark ,  Bernard Charles Drerup ,  Russell Dean Hoover ,  Charles Ray Johns ,  David John Krolak ,  Prasanna Srinivasan ,  Thuong Quang Truong

发明人： Gary Dale Carpenter ,  Scott Douglas Clark ,  Bernard Charles Drerup ,  Russell Dean Hoover ,  Charles Ray Johns ,  David John Krolak ,  Prasanna Srinivasan ,  Thuong Quang Truong

IPC分类号： G06F12/00

CPC分类号： G06F12/0822

摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system.

摘要翻译： 一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。 本地节点确定请求是本地还是系统请求。 如果请求是本地请求，则执行本地节点中的目录的查找。 如果本地节点目录中的条目指示请求中的数据不具有远程所有者，并且请求没有远程目标，则在本地节点上解析数据的一致性，并且传输 如果需要，请求中指定的数据将被执行，并且请求是本地请求。 如果条目指示数据具有远程所有者或请求具有远程目标，则将请求转发到多节点系统中的所有远程节点。

公开(公告)号：US07260755B2

公开(公告)日：2007-08-21

申请号：US11071554

申请日：2005-03-03

申请人： Gary Dale Carpenter ,  Ramyanshu Datta

发明人： Gary Dale Carpenter ,  Ramyanshu Datta

IPC分类号： G01R31/28 ,  G06K5/04 ,  H03M13/00

CPC分类号： G01R31/31725 ,  G01R31/3016

摘要： An integrated circuit includes a testable delay path. A transition of a delay path input signal causes a subsequent transition of a delay path output signal. A pulse generator receives the delay path input and output signals and produces a pulse signal having a pulse width indicative of the delay between the delay path input and output signal transitions. A delay line receives the pulse signal from the pulse generator. The delay line generates information indicative of the pulse signal pulse width. The delay line may include multiple stages in series where each stage reduces the pulse width of the pulse signal. The delay line may include a high skew inverter having PMOS and NMOS transistors having significantly different gains. The pulse generator is configured to produce a positive going pulse signal regardless of whether the delay path is inverting or non-inverting.

摘要翻译： 集成电路包括可测试延迟路径。 延迟路径输入信号的转变导致延迟路径输出信号的随后转变。 脉冲发生器接收延迟路径输入和输出信号并产生具有指示延迟路径输入和输出信号转换之间的延迟的脉冲宽度的脉冲信号。 延迟线从脉冲发生器接收脉冲信号。 延迟线产生指示脉冲信号脉冲宽度的信息。 延迟线可以包括串联的多个级，其中每级降低脉冲信号的脉冲宽度。 延迟线可以包括具有PMOS和NMOS晶体管的具有显着不同增益的高偏斜反相器。 脉冲发生器被配置为产生正向脉冲信号，而不管延迟路径是反相还是反相。

公开(公告)号：US06710668B1

公开(公告)日：2004-03-23

申请号：US10242256

申请日：2002-09-12

申请人： Gary Dale Carpenter ,  Hung Cai Ngo ,  Ivan Vo

发明人： Gary Dale Carpenter ,  Hung Cai Ngo ,  Ivan Vo

IPC分类号： H03B520

CPC分类号： H03K3/0315

摘要： According to an apparatus form of the invention, oscillator circuitry for operating a number of inverters in a loop (also known as a “ring”) includes a number of inverters. The inverters include a series of M inverters and a series of N inverters. The M inverters have signal propagation delay of m and the N inverters have signal propagation delay of n. The circuitry also includes means for selecting whether to exclude the N inverters from operating in the loop operable for receiving a select signal on a data input. The selecting means times assertion of the select signal on an output to select the number of inverters. In order to glitchlessly change the number of inverters operating in the loop, the selecting means has a certain delay greater than delay n.

摘要翻译： 根据本发明的装置形式，用于在环路（也称为“环”）中操作多个逆变器的振荡器电路包括多个逆变器。 逆变器包括一系列M个逆变器和一系列N个逆变器。 M个反相器具有m的信号传播延迟，N个反相器具有n的信号传播延迟。 电路还包括用于选择是否排除N个反相器在循环中操作以用于接收数据输入上的选择信号的装置。 选择装置在输出端上选择选择信号的次数来选择反相器的数量。 为了无缝地改变在循环中工作的逆变器的数量，选择装置具有大于延迟n的一定延迟。

公开(公告)号：US06192452B1

公开(公告)日：2001-02-20

申请号：US09259378

申请日：1999-02-26

申请人： John Peyton Bannister ,  Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

发明人： John Peyton Bannister ,  Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G06F1200

CPC分类号： G06F12/0813

摘要： A method for avoiding data loss due to cancelled transactions within a non-uniform memory access (NUMA) data processing system is disclosed. A NUMA data processing system includes a node interconnect to which at least a first node and a second node are coupled. The first and the second nodes each includes a local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and a node interconnect. The node controller detects certain situations which, due to the nature of a NUMA data processing system, can lead to data loss. These situations share the common feature that a node controller ends up with the only copy of a modified cache line and the original transaction that requested the modified cache line may not be issued again with the same tag or may not be issued again at all. The node controller corrects these situations by issuing its own write transaction to the system memory for that modified cache line using its own tag, and then providing the data the modified cache line is holding. This ensures that the modified data will be written to the system memory.

摘要翻译： 公开了一种用于避免由于在非均匀存储器访问（NUMA）数据处理系统中被取消的事务而导致的数据丢失的方法。 NUMA数据处理系统包括至少第一节点和第二节点耦合到的节点互连。 第一和第二节点各自包括本地互连，耦合到本地互连的系统存储器和插入在本地互连和节点互连之间的节点控制器。 节点控制器检测某些情况，由于NUMA数据处理系统的性质，可能导致数据丢失。 这些情况共享了节点控制器以修改的高速缓存行的唯一副本结束的共同特征，并且请求修改的高速缓存行的原始事务可能不会以相同的标签重新发出，也可能根本不再发出。 节点控制器通过使用其自己的标签向修改的高速缓存行发出自己的写入事务来修正这些情况，然后提供修改后的高速缓存行正在保存的数据。 这样可以确保将修改后的数据写入系统内存。

公开(公告)号：US09251913B2

公开(公告)日：2016-02-02

申请号：US13156836

申请日：2011-06-09

申请人： Gary Dale Carpenter ,  Alan James Drake ,  Eren Kursun ,  Phillip John Restle

发明人： Gary Dale Carpenter ,  Alan James Drake ,  Eren Kursun ,  Phillip John Restle

IPC分类号： G01R27/28 ,  G11C29/02 ,  G01R31/28 ,  G11C7/10 ,  H01L25/065 ,  G11C29/50

CPC分类号： G11C29/025 ,  G01R31/2882 ,  G11C7/10 ,  G11C29/50012 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.

摘要翻译： 在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的基础设施的方法和系统。 关键路径监控电路（基础设施）被配置为从第一层中的发射点发射信号，第一层是第一电路。 基础设施还被配置为创建到捕获点的电路径。 信号从第一层的发射点发射。 测量电路径的性能特征，从而进行测量，其中测量表示当与3D堆叠中的第二层堆叠时的第一层的性能，而不会在3D堆叠中实际堆叠第一层和第二层 ，第二层是第二电路。

公开(公告)号：US06269428B1

公开(公告)日：2001-07-31

申请号：US09259367

申请日：1999-02-26

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

IPC分类号： G06F1200

CPC分类号： G06F12/0828 ,  G06F12/0813

摘要： A method for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system is disclosed. A NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to a request by a processor of a first node to invalidate a remote copy of a cache line also stored within its cache memory at substantially the same time when a processor of a second node is also requesting to invalidate said cache line, one of the two requests is allowed to complete. The allowed request is the first request to complete without retry at the point of coherency, typically the home node. Subsequently, the other one of the two requests is permitted to complete.

摘要翻译： 公开了一种用于避免由于在非均匀存储器访问系统内的无效事务的冲突而导致的活动锁定的方法。 NUMA计算机系统包括耦合到互连的至少两个节点。 两个节点中的每一个包括本地系统存储器。 响应于第一节点的处理器在第二节点的处理器也要求使所述高速缓存行无效的基本上同时存储在其高速缓冲存储器中的高速缓存行的远端副本的请求时， 这两个请求被允许完成。 允许的请求是第一个完成的请求，而不是在一致性的时候重试，通常是家庭节点。 随后，两个请求中的另一个被允许完成。

公开(公告)号：US6145032A

公开(公告)日：2000-11-07

申请号：US157894

申请日：1998-09-21

申请人： John Peyton Bannister ,  Gary Dale Carpenter ,  David Brian Glasco

发明人： John Peyton Bannister ,  Gary Dale Carpenter ,  David Brian Glasco

IPC分类号： H04L12/56 ,  G06F3/00

CPC分类号： H04L49/901 ,  H04L49/90 ,  H04L49/9031

摘要： A data recirculation apparatus for a data processing system includes at least one output buffer from which data are output onto an interconnect, a plurality of input storage areas from which data are selected for storage within the output buffer, and selection logic that selects data from the plurality of input storage areas for storage within the output buffer. In addition, the data recirculation apparatus includes buffer control logic that, in response to a determination that a particular datum has stalled in the output buffer, causes the particular datum to be removed from the output buffer and stored in one of the plurality of input storage areas. In one embodiment, the recirculated data has a dedicated input storage area.

摘要翻译： 用于数据处理系统的数据再循环装置包括至少一个输出缓冲器，数据从该输出缓冲器输出到互连上，多个输入存储区域，数据被选择用于存储在输出缓冲器内;以及选择逻辑，其从 多个输入存储区域用于存储在输出缓冲器内。 此外，数据再循环装置包括缓冲器控制逻辑，其响应于确定特定数据在输出缓冲器中停滞而导致特定数据从输出缓冲器中移除并存储在多个输入存储器 地区 在一个实施例中，再循环数据具有专用输入存储区域。