公开(公告)号：US5906948A

公开(公告)日：1999-05-25

申请号：US062358

申请日：1998-04-17

申请人： Hao-Chieh Liu ,  Erik S. Jeng

发明人： Hao-Chieh Liu ,  Erik S. Jeng

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/3065

CPC分类号： H01L21/31116 ,  H01L21/76816

摘要： A method for etching dielectric layers is disclosed. A first etch of the dielectric layers is performed with a gas chemistry comprising C.sub.4 F.sub.8 flowing at about 10 sccm to about 25 sccm and CH.sub.3 F flowing at about 5 sccm to about 20 sccm. A second etch of the dielectric layers is performed with the gas chemistry and flow rates of gases which are about 10% to about 40% greater than the flow rates of gases in the first etch.

摘要翻译： 公开了蚀刻电介质层的方法。 电介质层的第一次蚀刻是用包含以约10sccm至约25sccm流动的C 4 F 8的气体化学物质和以约5sccm至约20sccm流动的CH 3 F进行的。 介电层的第二次蚀刻是通过气体化学和气体流速比第一蚀刻中的气体流速大约10％至大约40％进行的。

公开(公告)号：US5904521A

公开(公告)日：1999-05-18

申请号：US919393

申请日：1997-08-28

申请人： Erik S. Jeng ,  Yue-Feng Chen

发明人： Erik S. Jeng ,  Yue-Feng Chen

IPC分类号： H01L21/8242

CPC分类号： H01L27/10852

摘要： A method for forming a contact hole of a capacitor of a DRAM cell is disclosed. The method includes forming a first conductive layer on a semiconductor substrate, and forming a first dielectric layer on the first conductive layer. After patterning to etch the first dielectric layer and the first conductive layer, a second dielectric layer is formed on the semiconductor substrate and the first dielectric layer. Next, the second dielectric layer is anisotropically etched back to form a first spacer on sidewalls of the first dielectric layer and the first conductive layer. A first silicon oxide layer is formed over the semiconductor substrate, the first dielectric layer, the first spacer, followed by patterning to etch the first silicon oxide layer, wherein the first spacer and the first dielectric layer are used for facilitating self-aligned etching. Thereafter, a second conductive layer is formed over the semiconductor substrate, wherein surface of the first silicon oxide layer is exposed, and a second silicon oxide layer is formed over the second conductive layer and the first silicon oxide layer. Finally, patterning to etch a portion of the second silicon oxide layer to expose a portion of the second conductive layer, therefore a contact hole of the capacitor is formed.

摘要翻译： 公开了一种用于形成DRAM单元的电容器的接触孔的方法。 该方法包括在半导体衬底上形成第一导电层，并在第一导电层上形成第一介电层。 在图案化以蚀刻第一介电层和第一导电层之后，在半导体衬底和第一介电层上形成第二电介质层。 接下来，第二介电层被各向异性地回蚀以在第一介电层和第一导电层的侧壁上形成第一间隔物。 在半导体衬底上形成第一氧化硅层，第一介电层，第一间隔物，然后构图以蚀刻第一氧化硅层，其中第一间隔物和第一介电层用于促进自对准蚀刻。 此后，在半导体衬底上形成第二导电层，其中露出第一氧化硅层的表面，并在第二导电层和第一氧化硅层上形成第二氧化硅层。 最后，图案化以蚀刻第二氧化硅层的一部分以暴露第二导电层的一部分，因此形成电容器的接触孔。

公开(公告)号：US5804852A

公开(公告)日：1998-09-08

申请号：US876914

申请日：1997-06-16

申请人： Fu-Liang Yang ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Erik S. Jeng

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A multiple crown shaped polysilicon structure, used for a lower electrode of a DRAM stacked capacitor structure, has been developed. The multiple crown shaped, lower electrode, is formed overlying, and contacting a polysilicon fill layer, that is located between insulator encapsulated polycide gate structures. The polysilicon fill layer, in turn, contacts an underlying source/drain region of a transfer gate transistor. The multiple crown shaped lower electrode is comprised vertical polysilicon shapes, connected to an underlying, horizontal polysilicon shape, with the horizontal polysilicon shape overlying the polysilicon fill layer. One to three, vertical polysilicon shapes, are used on each side of the multiple crown shaped lower electrode.

摘要翻译： 已经开发了用于DRAM堆叠电容器结构的下电极的多冠状多晶硅结构。 形成多个冠状的下电极，其位于绝缘体封装的多晶硅栅极结构之间，覆盖并接触多晶硅填充层。 多晶硅填充层又接触传输栅晶体管的底层源/漏区。 多冠状下电极包括垂直多晶硅形状，连接到下面的水平多晶硅形状，其中水平多晶硅形状覆盖多晶硅填充层。 在多冠状下电极的每一侧使用一至三个垂直多晶硅形状。

公开(公告)号：US5804489A

公开(公告)日：1998-09-08

申请号：US679196

申请日：1996-07-12

申请人： Fu-Liang Yang ,  Erik S. Jeng ,  Yu-Chun Ho ,  Bin Liu ,  Chao-Ming Koh

发明人： Fu-Liang Yang ,  Erik S. Jeng ,  Yu-Chun Ho ,  Bin Liu ,  Chao-Ming Koh

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The present invention is a method of manufacturing crown shape capacitors in the semiconducter memories. Using a single step etching to farbricate the capacitor in a DRAM cell. The method can form side wall polymers and etching byproductions on the surface of the first polysilicon, using the side wall polymers and the etching byproductions as a mask to form the crown shape capacitors with pillars. Moreover, this present invention can form the crown shape structure and pillars in the same step, the crown shape structure and the pillars increase the surface area of the capacitor. Therefore the present invention will increase the performance of the capacitor.

摘要翻译： 本发明是在半导体存储器中制造冠状电容器的方法。 使用单步蚀刻来超越DRAM单元中的电容器。 该方法可以使用侧壁聚合物和蚀刻副产物作为掩模形成侧壁聚合物并在第一多晶硅的表面上蚀刻副产物，以形成具有支柱的冠状电容器。 此外，本发明可以在相同的步骤中形成冠状结构和柱，冠状结构和柱增加电容器的表面积。 因此，本发明将增加电容器的性能。

公开(公告)号：US5792689A

公开(公告)日：1998-08-11

申请号：US827817

申请日：1997-04-11

申请人： Fu-Liang Yang ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Erik S. Jeng

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method is described using a single photoresist mask to make a double-crown-shaped DRAM capacitor self-aligned to the capacitor node contact. After forming the DRAM FETs and the bit lines, a planar BPSG layer, a first polysilicon layer, and a CVD oxide layer are deposited. A node contact photoresist mask is used to form first openings in the CVD oxide in which silicon nitride sidewall spacers are formed. A smaller second opening is etched in the first opening to form node contact openings to the DRAM FET source/drain areas. A conformal second polysilicon layer is deposited to form node contacts in the second openings and over the free-standing sidewall spacers. A planar spin-on glass layer is then used as a self-aligned mask to etch back to expose the second polysilicon layer, which is then removed from the top of the sidewall spacers. After removing the spin-on glass an anisotropic etch is used to form the double-crown-shaped capacitor bottom electrodes self-aligned to the node contacts. The bottom electrode surface is roughened to increase the capacitance area, and the sidewall spacers are removed. An interelectrode dielectric layer and a third polysilicon layer are used to complete the double-crown-shaped stacked capacitors.

摘要翻译： 使用单个光致抗蚀剂掩模描述一种方法，以使双冠形DRAM电容器与电容器节点接触自对准。 在形成DRAM FET和位线之后，沉积平面BPSG层，第一多晶硅层和CVD氧化物层。 使用节点接触光刻胶掩模在其中形成氮化硅侧壁间隔物的CVD氧化物中形成第一开口。 在第一开口中蚀刻较小的第二开口以形成到DRAM FET源极/漏极区域的节点接触开口。 沉积保形第二多晶硅层以在第二开口中并且在独立的侧壁间隔物上形成节点接触。 然后将平面旋涂玻璃层用作自对准掩模以回蚀以暴露第二多晶硅层，然后从侧壁间隔物的顶部除去第二多晶硅层。 在去除旋涂玻璃之后，使用各向异性蚀刻来形成与节点接触自对准的双冠状电容器底部电极。 底部电极表面被粗糙化以增加电容面积，并且去除侧壁间隔物。 使用电极间电介质层和第三多晶硅层来完成双冠形叠层电容器。

公开(公告)号：US06903968B2

公开(公告)日：2005-06-07

申请号：US10763773

申请日：2004-01-22

申请人： Erik S. Jeng

发明人： Erik S. Jeng

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/792 ,  G11C16/04

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7923

摘要： A nonvolatile memory capable of storing multi-bits binary information is provided. The memory includes an oxide formed on a substrate. A control gate is formed on the oxide. An L-shape structure is attached on sidewall of the control gate. Spacers are formed on the L-shape structure to act as a floating gate. A first doped region and a second doped region is formed in the substrate adjacent to the spacers with a channel between the two doped regions. Wherein the spacer represent a first binary status by injecting and storing electrical charges in the spacers. Or to represent a second binary status by not injecting electrical charges into the spacer.

摘要翻译： 提供了能够存储多位二进制信息的非易失性存储器。 存储器包括形成在衬底上的氧化物。 在氧化物上形成控制栅极。 L型结构附着在控制门的侧壁上。 间隔件形成在L形结构上以充当浮动门。 第一掺杂区域和第二掺杂区域在与衬垫相邻的衬底中在两个掺杂区域之间具有沟道形成。 其中间隔物通过在间隔物中注入和储存电荷而代表第一二进制状态。 或者通过不将间隔器中的电荷注入来表示第二二进制状态。

公开(公告)号：US06278189B1

公开(公告)日：2001-08-21

申请号：US09428571

申请日：1999-10-28

申请人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

发明人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

IPC分类号： H01L2348

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.

摘要翻译： 公开了一种在高密度集成电路中制造接触孔的方法及其结构。 显示出通过明智地整合形成浅锥形孔的过程与自对准技术，可以以减少数量的掩模处理步骤来制造自对准的孔。 这是通过首先通过各向同性蚀刻在衬底中的某些区域上形成一定深度的浅锥形孔，然后通过各向异性蚀刻将它们扩展到对应于它们允许接触的区域的全深度来实现的。 最终的结果是整套孔是自对准的并且通过单个光致抗蚀剂掩模形成。

公开(公告)号：US6136661A

公开(公告)日：2000-10-24

申请号：US332430

申请日：1999-06-14

申请人： Tzu-Shih Yen ,  Erik S. Jeng

发明人： Tzu-Shih Yen ,  Erik S. Jeng

IPC分类号： G03F7/40 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/92 ,  G03F7/405 ,  H01L21/0273 ,  H01L21/32139 ,  H01L27/10852

摘要： A method of fabrication of a storage capacitors for DRAM memory cells using silylated photoresist is described. Partially completed DRAM memory cells comprising wordline transistor gates and bitline source and drain regions is provided. Conductive plugs are provided through a dielectric layer to the top surfaces of the bitline drain regions. A first conductive layer is deposited overlying the conductive plugs. A photoresist layer is deposited overlying the first conductive layer. The photoresist layer is etched to define the areas for the lower plates of the storage capacitors. The photoresist is exposed to a silylating agent to form a silylated layer. The top layer of the silylated photoresist is etched through to form a mask for subsequent etching. The photoresist layer is etched as defined by the mask. The first conductive layer is etched as defined by the mask to form the shape of the lower nodes of the storage capacitors. The remaining silylated photoresist is removed. A capacitor dielectric layer is deposited overlying the lower nodes of the storage capacitors. A second conductive layer is deposited to form the upper nodes of the storage capacitors. A passivation layer is deposited to complete fabrication.

摘要翻译： 描述了使用甲硅烷基化光致抗蚀剂制造用于DRAM存储单元的存储电容器的方法。 提供了包括字线晶体管栅极和位线源极和漏极区域的部分完成的DRAM存储单元。 导电插头通过电介质层提供到位线漏极区域的顶表面。 第一导电层沉积在导电塞上。 沉积在第一导电层上的光致抗蚀剂层。 蚀刻光致抗蚀剂层以限定存储电容器的下板的区域。 将光致抗蚀剂暴露于甲硅烷基化剂以形成甲硅烷基化层。 硅烷化光致抗蚀剂的顶层被蚀刻通过以形成用于后续蚀刻的掩模。 如由掩模所限定的那样蚀刻光致抗蚀剂层。 如由掩模限定的那样蚀刻第一导电层以形成存储电容器的下部结点的形状。 除去剩余的甲硅烷基化光致抗蚀剂。 电容器介质层沉积在存储电容器的下部结点上。 沉积第二导电层以形成存储电容器的上部节点。 沉积钝化层以完成制造。

公开(公告)号：US6037276A

公开(公告)日：2000-03-14

申请号：US958462

申请日：1997-10-27

申请人： Hua-Tai Lin ,  Erik S. Jeng ,  Liang-Gi Yao

发明人： Hua-Tai Lin ,  Erik S. Jeng ,  Liang-Gi Yao

IPC分类号： H01L21/3213 ,  H01L21/31

CPC分类号： H01L21/32139

摘要： A method for improving the patterning process of a conductive layer using a dual-layer cap of oxynitride and silicon nitride. The oxynitride layer acts as a BARC (Bottom Anti-Reflective Coating) to improve photolithography process performance. The oxynitride is formed by plasma-enhanced chemical vapor deposition.

摘要翻译： 使用氮氧化硅和氮化硅的双层盖来改善导电层的图案化工艺的方法。 氧氮化物层用作BARC（底部防反射涂层）以改善光刻工艺性能。 氧氮化物通过等离子体增强化学气相沉积形成。

公开(公告)号：US06001704A

公开(公告)日：1999-12-14

申请号：US90720

申请日：1998-06-04

申请人： Hsu-Li Cheng ,  Erik S. Jeng ,  Wei-Ray Lin

发明人： Hsu-Li Cheng ,  Erik S. Jeng ,  Wei-Ray Lin

IPC分类号： H01L21/308 ,  H01L21/314 ,  H01L21/762 ,  H01L21/76 ,  H01L21/425

CPC分类号： H01L21/3081 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/3143

摘要： A stacked layer including a first oxide, a nitride layer, a second oxide layer and an oxynitride layer is formed on the top of the first oxide layer. An etching is performed through a photoresist to etch the oxynitride, the second oxide and nitride. Oxide spacers are formed on the side walls of the pattern structure, the oxynitride layer is also removed during the formation of the oxide spacers. Trenches are generated by a dry etching technique. The second oxide and the oxide spacers are removed. Next, a thermal oxidation is performed to rounding the corners of the trench openings. A gap filling material is refilled into the trenches and formed on the nitride. Next, a chemical mechanical polishing (CMP) is used to remove the top of the CVD-oxide and the nitride layer. The residual nitride layer, the CVD-oxide and pad oxide are removed to create trench isolation structures with rounding corners.

摘要翻译： 在第一氧化物层的顶部形成包括第一氧化物，氮化物层，第二氧化物层和氧氮化物层的层叠层。 通过光致抗蚀剂进行蚀刻以蚀刻氧氮化物，第二氧化物和氮化物。 在图案结构的侧壁上形成氧化物间隔物，在形成氧化物间隔物期间也去除氧氮化物层。 通过干蚀刻技术产生沟槽。 去除第二氧化物和氧化物间隔物。 接下来，进行热氧化以对沟槽开口的角进行四舍五入。 间隙填充材料再填充到沟槽中并形成在氮化物上。 接下来，使用化学机械抛光（CMP）来除去CVD氧化物和氮化物层的顶部。 去除残余氮化物层，CVD氧化物和衬垫氧化物以产生具有圆角的沟槽隔离结构。