公开(公告)号：US06278189B1

公开(公告)日：2001-08-21

申请号：US09428571

申请日：1999-10-28

申请人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

发明人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

IPC分类号： H01L2348

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.

摘要翻译： 公开了一种在高密度集成电路中制造接触孔的方法及其结构。 显示出通过明智地整合形成浅锥形孔的过程与自对准技术，可以以减少数量的掩模处理步骤来制造自对准的孔。 这是通过首先通过各向同性蚀刻在衬底中的某些区域上形成一定深度的浅锥形孔，然后通过各向异性蚀刻将它们扩展到对应于它们允许接触的区域的全深度来实现的。 最终的结果是整套孔是自对准的并且通过单个光致抗蚀剂掩模形成。

公开(公告)号：US5994228A

公开(公告)日：1999-11-30

申请号：US827818

申请日：1997-04-11

申请人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

发明人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L21/00 ,  H01L21/70

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002

摘要： A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.

摘要翻译： 公开了一种在高密度集成电路中制造接触孔的方法及其结构。 显示出通过明智地整合形成浅锥形孔的过程与自对准技术，可以以减少数量的掩模处理步骤来制造自对准的孔。 这是通过首先通过各向同性蚀刻在衬底中的某些区域上形成一定深度的浅锥形孔，然后通过各向异性蚀刻将它们扩展到对应于它们允许接触的区域的全深度来实现的。 最终的结果是整套孔是自对准的并且通过单个光致抗蚀剂掩模形成。

公开(公告)号：US6140240A

公开(公告)日：2000-10-31

申请号：US226275

申请日：1999-01-07

申请人： Fu-Liang Yang ,  Bih-Tiao Lin ,  Tzu-Shih Yen ,  Bi-Ling Chen ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Bih-Tiao Lin ,  Tzu-Shih Yen ,  Bi-Ling Chen ,  Erik S. Jeng

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L21/31053 ,  H01L21/31138

摘要： A method of removing microscratches in planarized dielectric surfaces covering conductor layers in submicron integrated circuit structures includes a semiconductor substrate having at least one dielectric layer formed thereon followed by a chemical mechanical polishing process for planarization. The removal of microscratches includes depositing a PE-CVD polymer layer to fill the microscratches, caused by CMP planarization, and to cover the planarized dielectric surface with a thin layer of the polymer. Deposition is followed by introducing an etching gas into the CVD chamber for an etch back of the just deposited polymer to well below the depth of the microscratches wherein the deposited polymer has the same etch rate as the dielectric layer formed thereunder.

摘要翻译： 在亚微米集成电路结构中的覆盖导体层的平坦化电介质表面中去除微结构的方法包括具有形成在其上的至少一个介电层，然后进行平面化的化学机械抛光工艺的半导体衬底。 去除微观尺度包括沉积PE-CVD聚合物层以填充由CMP平坦化引起的微观尺度，并用聚合物薄层覆盖平坦化的电介质表面。 沉积之后，将CVD蚀刻气体引入CVD室，以便正好沉积的聚合物的蚀刻深度远低于微细凹槽的深度，其中沉积的聚合物具有与其下形成的介电层相同的蚀刻速率。

公开(公告)号：US07457154B2

公开(公告)日：2008-11-25

申请号：US11445205

申请日：2006-06-02

申请人： Tzu-shih Yen ,  Erik S. Jeng

发明人： Tzu-shih Yen ,  Erik S. Jeng

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/112 ,  H01L27/115 ,  H01L29/4234 ,  H01L29/7923

摘要： A memory system comprising a memory array having a plurality of memory units, a column decoder, a row decoder, a selecting/driving circuit and a sensing circuit is disclosed. Each memory unit comprises a gate electrode coupled to a word lines, a source region coupled to a source line or a first bit line, a drain region coupled to a drain line or a second bit line, a first spacer between the source region and the gate electrode and a second spacer between the drain region and the gate electrode. When a first-bit program operation is performed on the memory unit, a switch-on signal is applied to the gate, a programming signal is applied to the source region and the drain region is switched to ground. As the memory unit is activated, the carriers are injected and stored in a first spacer, thus represents a first bit in the memory unit.

摘要翻译： 一种存储器系统，包括具有多个存储器单元的存储器阵列，列解码器，行解码器，选择/驱动电路和感测电路。 每个存储器单元包括耦合到字线的栅电极，耦合到源极线或第一位线的源极区域，耦合到漏极线或第二位线的漏极区域，源区域和第二位线之间的第一间隔物 栅极电极和漏极区域和栅电极之间的第二间隔物。 当对存储器单元执行第一位编程操作时，将接通信号施加到栅极，将编程信号施加到源极区域，并将漏极区域切换到地。 当存储器单元被激活时，载体被注入并存储在第一间隔件中，因此代表存储器单元中的第一位。

公开(公告)号：US06306759B1

公开(公告)日：2001-10-23

申请号：US09654928

申请日：2000-09-05

申请人： Tzu-Shih Yen ,  Erik S. Jeng ,  Hsiao-Chin Tuan ,  Chun-Yao Chen ,  Eddy Chiang ,  Wen-Shiang Liao

发明人： Tzu-Shih Yen ,  Erik S. Jeng ,  Hsiao-Chin Tuan ,  Chun-Yao Chen ,  Eddy Chiang ,  Wen-Shiang Liao

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/76831

摘要： A method for forming self-aligned contact (SAC) is disclosed to improve device reliability. The method includes forming a dielectric liner over the contact opening before the contact plug is filled in. Optional contact implantation before and after the liner formation can be added to enhance the doping profile of the device.

摘要翻译： 公开了一种用于形成自对准接触（SAC）的方法，以提高器件的可靠性。 该方法包括在接触插塞填充之前在接触开口上形成电介质衬垫。可以添加在衬垫形成之前和之后的可选接触注入以增强器件的掺杂特性。

公开(公告)号：US6136661A

公开(公告)日：2000-10-24

申请号：US332430

申请日：1999-06-14

申请人： Tzu-Shih Yen ,  Erik S. Jeng

发明人： Tzu-Shih Yen ,  Erik S. Jeng

IPC分类号： G03F7/40 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/92 ,  G03F7/405 ,  H01L21/0273 ,  H01L21/32139 ,  H01L27/10852

摘要： A method of fabrication of a storage capacitors for DRAM memory cells using silylated photoresist is described. Partially completed DRAM memory cells comprising wordline transistor gates and bitline source and drain regions is provided. Conductive plugs are provided through a dielectric layer to the top surfaces of the bitline drain regions. A first conductive layer is deposited overlying the conductive plugs. A photoresist layer is deposited overlying the first conductive layer. The photoresist layer is etched to define the areas for the lower plates of the storage capacitors. The photoresist is exposed to a silylating agent to form a silylated layer. The top layer of the silylated photoresist is etched through to form a mask for subsequent etching. The photoresist layer is etched as defined by the mask. The first conductive layer is etched as defined by the mask to form the shape of the lower nodes of the storage capacitors. The remaining silylated photoresist is removed. A capacitor dielectric layer is deposited overlying the lower nodes of the storage capacitors. A second conductive layer is deposited to form the upper nodes of the storage capacitors. A passivation layer is deposited to complete fabrication.

摘要翻译： 描述了使用甲硅烷基化光致抗蚀剂制造用于DRAM存储单元的存储电容器的方法。 提供了包括字线晶体管栅极和位线源极和漏极区域的部分完成的DRAM存储单元。 导电插头通过电介质层提供到位线漏极区域的顶表面。 第一导电层沉积在导电塞上。 沉积在第一导电层上的光致抗蚀剂层。 蚀刻光致抗蚀剂层以限定存储电容器的下板的区域。 将光致抗蚀剂暴露于甲硅烷基化剂以形成甲硅烷基化层。 硅烷化光致抗蚀剂的顶层被蚀刻通过以形成用于后续蚀刻的掩模。 如由掩模所限定的那样蚀刻光致抗蚀剂层。 如由掩模限定的那样蚀刻第一导电层以形成存储电容器的下部结点的形状。 除去剩余的甲硅烷基化光致抗蚀剂。 电容器介质层沉积在存储电容器的下部结点上。 沉积第二导电层以形成存储电容器的上部节点。 沉积钝化层以完成制造。

公开(公告)号：US06265296B1

公开(公告)日：2001-07-24

申请号：US09436688

申请日：1999-11-08

申请人： Tzu-Shih Yen ,  Erik S. Jeng ,  Hao-Chieh Liu ,  Hung-Yi Luo

发明人： Tzu-Shih Yen ,  Erik S. Jeng ,  Hao-Chieh Liu ,  Hung-Yi Luo

IPC分类号： H01L213205

CPC分类号： H01L21/76897 ,  H01L21/31144

摘要： A method for making self-aligned contacts on a semiconductor substrate using a hard mask. After the transistor is formed, a blanket insulating layer is formed on said semiconductor substrate. A hard mask having openings on the blanket insulating layer is formed over the insulating layer. The openings overlay the source/drain region and part of the gate electrode structure. Using the patterned hard mask, the insulating layer is etched to the gate electrode protecting layer. Then self-aligned contacts is completed by etching the insulating layer to expose the source/drain regions using the gate electrode protecting layer and the insulating sidewall spacers as the mask.

摘要翻译： 一种使用硬掩模在半导体衬底上进行自对准接触的方法。 在形成晶体管之后，在所述半导体衬底上形成覆盖绝缘层。 在绝缘层上形成有在绝缘层上具有开口的硬掩模。 开口覆盖源极/漏极区域和栅电极结构的一部分。 使用图案化的硬掩模，将绝缘层蚀刻到栅电极保护层。 然后通过蚀刻绝缘层来完成自对准触点，以使用栅电极保护层和绝缘侧壁间隔件作为掩模来暴露源/漏区。

公开(公告)号：US06124192A

公开(公告)日：2000-09-26

申请号：US405062

申请日：1999-09-27

申请人： Erik S. Jeng ,  Tzu-Shih Yen ,  Hung-Yi Luo

发明人： Erik S. Jeng ,  Tzu-Shih Yen ,  Hung-Yi Luo

IPC分类号： H01L21/60 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002

摘要： A process for fabricating an interconnect structure, featuring contact of the interconnect structure, to an exposed side of an underlying conductive plug structure, where the conductive plug structure is used to communicate with an active device region in a semiconductor substrate, has been developed. The process features the use of simple photolithographic patterns, such as a stripe opening, exposing a group of gate structures, and a group of spaces, located between the gate structures, to be used for subsequent contact plug formation. This is in contrast to conventional processing, in which a more difficult photolithographic procedure is used to create smaller, individual openings, to individual spaces between gate structures. In addition this invention features a self-aligned opening, exposing only a side of a contact plug structure. An overlying interconnect structure then contacts only the exposed side of the underlying contact plug structure, again reducing photolithographic difficulties, encountered with conventional methods of creating a non-self aligned opening to an underlying contact plug.

摘要翻译： 已经开发了用于制造互连结构的方法，该互连结构具有互连结构的接触到底层导电插塞结构的暴露侧，其中导电插塞结构用于与半导体衬底中的有源器件区域连通。 该方法特征在于使用简单的光刻图案，例如条形开口，暴露一组栅极结构，以及位于栅极结构之间的一组空间，用于随后的接触插塞形成。 这与常规处理相反，其中使用更困难的光刻工艺来为门结构之间的各个空间创建更小的单个开口。 此外，本发明具有自对准开口，仅暴露接触插塞结构的一侧。 上覆的互连结构然后仅接触下面的接触插塞结构的暴露侧，再次降低光刻困难，这与传统的向下面的接触插塞产生非自对准开口的方法相碰。

公开(公告)号：US5962195A

公开(公告)日：1999-10-05

申请号：US926785

申请日：1997-09-10

申请人： Tzu-Shih Yen ,  Erik S. Jeng

发明人： Tzu-Shih Yen ,  Erik S. Jeng

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  G03F7/00

CPC分类号： H01L21/28123 ,  H01L21/0276 ,  H01L21/0338 ,  H01L21/32139

摘要： A method for forming a patterned target layer within an integrated circuit. The method employs a plasma pre-treatment of a patterned photoresist layer employed in patterning a blanket focusing which in turn is employed in patterning the patterned target layer from a blanket target layer. The plasma pre-treatment employs a plasma pre-treatment composition comprising carbon tetrafluoride and argon without oxygen. After the plasma pre-treatment, the blanket focusing layer is etched with a reproducible negative etch bias in a plasma etch method employing an etchant gas composition comprising carbon tetrafluoride and argon without oxygen. Through the method there may be formed patterned target layers, with enhanced uniformity, of linewidth dimension as narrow as about of 0.25 microns while employing near ultra-violet (NUV) (ie: 365 nm) photoexposure methods.

摘要翻译： 一种在集成电路内形成图案化目标层的方法。 该方法采用对图案化覆层聚焦进行图案化光刻胶层的等离子体预处理，该毯聚焦又用于从覆盖目标层图案化图案化目标层。 等离子体预处理采用包含四氟化碳和无氧的氩的等离子体预处理组合物。 在等离子体预处理之后，使用包含四氟化碳和无氧的氩气的蚀刻剂气体组合物的等离子体蚀刻方法，以可再现的负蚀刻偏压蚀刻覆盖层聚焦层。 通过该方法，可以使用近紫外（NUV）（即：365nm）光曝光方法形成线宽尺寸的图案化目标层，具有增强的均匀性，其宽度大约为0.25微米。

公开(公告)号：US06376384B1

公开(公告)日：2002-04-23

申请号：US09557398

申请日：2000-04-24

申请人： Tzu-Shih Yen ,  Erik S. Jeng ,  I-Ping Lee ,  Eddy Chiang

发明人： Tzu-Shih Yen ,  Erik S. Jeng ,  I-Ping Lee ,  Eddy Chiang

IPC分类号： H01L21302

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76897 ,  Y10S438/963

摘要： A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and oxygen. The method may also be employed in general for etching silicon oxide layers in the presence of silicon nitride layers. Similarly, the method may also in general be employed in removing fluorocarbon polymer residue layers from integrated circuit layers including but not limited to silicon oxide layers and silicon nitride layers.

摘要翻译： 一种通过氧化硅层形成通孔的方法。 首先提供基板。 然后在衬底上形成图案化的氮化硅层，其限定图案化氮化硅层下面的接触区域。 然后在图案化的氮化硅层上形成氧化硅层。 然后在使用包含氟碳化合物蚀刻剂气体的第一蚀刻剂气体组合物的反应离子蚀刻（RIE）方法的同时蚀刻氧化硅层，以形成：（1）蚀刻的氧化硅层，其暴露接触区域而基本上不蚀刻图案 氮化硅层; 和（2）在蚀刻的氧化硅层和图案化氮化硅层中的至少一个上形成的氟碳聚合物残渣层。 最后，使用包含碳氟化合物蚀刻剂气体和氧气的第二蚀刻剂气体组合物的下游等离子体蚀刻方法，从基底上剥离碳氟聚合物残余物层。 该方法通常也可用于在存在氮化硅层的情况下蚀刻氧化硅层。 类似地，该方法通常也可用于从包括但不限于氧化硅层和氮化硅层的集成电路层去除碳氟聚合物残余物层。