公开(公告)号：US08685825B2

公开(公告)日：2014-04-01

申请号：US13192378

申请日：2011-07-27

申请人： Daniel Tang ,  Tzu-Shih Yen

发明人： Daniel Tang ,  Tzu-Shih Yen

IPC分类号： H01L21/331 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/31053 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

摘要： A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

摘要翻译： 形成具有在源极区和漏极区之间具有源极区，漏极区和沟道区的鳍的finFET。 翅片在半导体晶片上蚀刻。 形成具有与沟道区域直接接触的绝缘层和与绝缘层直接接触的导电栅极材料的栅极堆叠。 蚀刻源极和漏极区域，离开鳍片的沟道区域。 外延半导体在与源极和漏极区相邻的沟道区的侧面生长以形成源外延区和漏极外延区。 源极和漏极外延区域在生长外延半导体的同时原位掺杂。

公开(公告)号：US06423646B1

公开(公告)日：2002-07-23

申请号：US09090627

申请日：1998-06-04

申请人： Tzu-Shih Yen ,  Hsiu-Lan Lee ,  Pei-Wen Li

发明人： Tzu-Shih Yen ,  Hsiu-Lan Lee ,  Pei-Wen Li

IPC分类号： H01L21302

CPC分类号： C11D11/0047 ,  C11D7/265 ,  C11D7/32 ,  C11D7/5004 ,  H01L21/02063

摘要： The present invention discloses a method for simultaneously removing from a silicon surface polymeric films and damaged silicon layers by exposing the surface to a cleaning solution that contains amine or ethanolamine for a length of time that is sufficient to remove all such unwanted materials. The method is effective in cleaning away damaged silicon layers having a thickness between about 20 Å and about 60 Å in a period of time between about 2 minutes and about 20 minutes. In a preferred embodiment, the cleaning solution is a water solution of ethanolamine and gallic acid.

摘要翻译： 本发明公开了一种通过将表面暴露于含有胺或乙醇胺的清洁溶液一段时间以足以除去所有这些不想要的材料的同时从硅表面除去硅表面聚合物膜和损坏的硅层的方法。 该方法在约2分钟至约20分钟之间的时间段内有效地清除具有约20埃至约60埃厚度的损坏的硅层。 在优选的实施方案中，清洗溶液是乙醇胺和没食子酸的水溶液。

公开(公告)号：US06265296B1

公开(公告)日：2001-07-24

申请号：US09436688

申请日：1999-11-08

申请人： Tzu-Shih Yen ,  Erik S. Jeng ,  Hao-Chieh Liu ,  Hung-Yi Luo

发明人： Tzu-Shih Yen ,  Erik S. Jeng ,  Hao-Chieh Liu ,  Hung-Yi Luo

IPC分类号： H01L213205

CPC分类号： H01L21/76897 ,  H01L21/31144

摘要： A method for making self-aligned contacts on a semiconductor substrate using a hard mask. After the transistor is formed, a blanket insulating layer is formed on said semiconductor substrate. A hard mask having openings on the blanket insulating layer is formed over the insulating layer. The openings overlay the source/drain region and part of the gate electrode structure. Using the patterned hard mask, the insulating layer is etched to the gate electrode protecting layer. Then self-aligned contacts is completed by etching the insulating layer to expose the source/drain regions using the gate electrode protecting layer and the insulating sidewall spacers as the mask.

摘要翻译： 一种使用硬掩模在半导体衬底上进行自对准接触的方法。 在形成晶体管之后，在所述半导体衬底上形成覆盖绝缘层。 在绝缘层上形成有在绝缘层上具有开口的硬掩模。 开口覆盖源极/漏极区域和栅电极结构的一部分。 使用图案化的硬掩模，将绝缘层蚀刻到栅电极保护层。 然后通过蚀刻绝缘层来完成自对准触点，以使用栅电极保护层和绝缘侧壁间隔件作为掩模来暴露源/漏区。

公开(公告)号：US06124192A

公开(公告)日：2000-09-26

申请号：US405062

申请日：1999-09-27

申请人： Erik S. Jeng ,  Tzu-Shih Yen ,  Hung-Yi Luo

发明人： Erik S. Jeng ,  Tzu-Shih Yen ,  Hung-Yi Luo

IPC分类号： H01L21/60 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002

摘要： A process for fabricating an interconnect structure, featuring contact of the interconnect structure, to an exposed side of an underlying conductive plug structure, where the conductive plug structure is used to communicate with an active device region in a semiconductor substrate, has been developed. The process features the use of simple photolithographic patterns, such as a stripe opening, exposing a group of gate structures, and a group of spaces, located between the gate structures, to be used for subsequent contact plug formation. This is in contrast to conventional processing, in which a more difficult photolithographic procedure is used to create smaller, individual openings, to individual spaces between gate structures. In addition this invention features a self-aligned opening, exposing only a side of a contact plug structure. An overlying interconnect structure then contacts only the exposed side of the underlying contact plug structure, again reducing photolithographic difficulties, encountered with conventional methods of creating a non-self aligned opening to an underlying contact plug.

摘要翻译： 已经开发了用于制造互连结构的方法，该互连结构具有互连结构的接触到底层导电插塞结构的暴露侧，其中导电插塞结构用于与半导体衬底中的有源器件区域连通。 该方法特征在于使用简单的光刻图案，例如条形开口，暴露一组栅极结构，以及位于栅极结构之间的一组空间，用于随后的接触插塞形成。 这与常规处理相反，其中使用更困难的光刻工艺来为门结构之间的各个空间创建更小的单个开口。 此外，本发明具有自对准开口，仅暴露接触插塞结构的一侧。 上覆的互连结构然后仅接触下面的接触插塞结构的暴露侧，再次降低光刻困难，这与传统的向下面的接触插塞产生非自对准开口的方法相碰。

公开(公告)号：US5962195A

公开(公告)日：1999-10-05

申请号：US926785

申请日：1997-09-10

申请人： Tzu-Shih Yen ,  Erik S. Jeng

发明人： Tzu-Shih Yen ,  Erik S. Jeng

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  G03F7/00

CPC分类号： H01L21/28123 ,  H01L21/0276 ,  H01L21/0338 ,  H01L21/32139

摘要： A method for forming a patterned target layer within an integrated circuit. The method employs a plasma pre-treatment of a patterned photoresist layer employed in patterning a blanket focusing which in turn is employed in patterning the patterned target layer from a blanket target layer. The plasma pre-treatment employs a plasma pre-treatment composition comprising carbon tetrafluoride and argon without oxygen. After the plasma pre-treatment, the blanket focusing layer is etched with a reproducible negative etch bias in a plasma etch method employing an etchant gas composition comprising carbon tetrafluoride and argon without oxygen. Through the method there may be formed patterned target layers, with enhanced uniformity, of linewidth dimension as narrow as about of 0.25 microns while employing near ultra-violet (NUV) (ie: 365 nm) photoexposure methods.

摘要翻译： 一种在集成电路内形成图案化目标层的方法。 该方法采用对图案化覆层聚焦进行图案化光刻胶层的等离子体预处理，该毯聚焦又用于从覆盖目标层图案化图案化目标层。 等离子体预处理采用包含四氟化碳和无氧的氩的等离子体预处理组合物。 在等离子体预处理之后，使用包含四氟化碳和无氧的氩气的蚀刻剂气体组合物的等离子体蚀刻方法，以可再现的负蚀刻偏压蚀刻覆盖层聚焦层。 通过该方法，可以使用近紫外（NUV）（即：365nm）光曝光方法形成线宽尺寸的图案化目标层，具有增强的均匀性，其宽度大约为0.25微米。

公开(公告)号：US5904154A

公开(公告)日：1999-05-18

申请号：US899669

申请日：1997-07-24

申请人： Rong-Wu Chien ,  Hsiu-Lan Lee ,  Tzu-Shih Yen

发明人： Rong-Wu Chien ,  Hsiu-Lan Lee ,  Tzu-Shih Yen

IPC分类号： G03F7/42 ,  H01L21/311 ,  H01L21/302 ,  B08B6/00

CPC分类号： H01L21/02063 ,  G03F7/427 ,  H01L21/31116

摘要： A method for removing from a patterned silicon containing dielectric layer a patterned partially fluorinated photoresist layer employed in patterning the patterned silicon containing dielectric layer. There is first formed over a semiconductor substrate a metal contact layer having a silicon containing dielectric layer formed thereover. There is then formed upon the silicon containing dielectric layer a patterned photoresist layer. There is then formed by use of a reactive ion etch (RIE) plasma etch method employing a fluorine containing etchant a via through the silicon containing dielectric layer to form a patterned silicon containing dielectric layer reaching the metal contact layer. The reactive ion etch (RIE) plasma etch method simultaneously forms from the patterned photoresist layer a partially fluorinated patterned photoresist layer comprising a patterned fluorinated surface layer of the partially fluorinated patterned photoresist layer and a patterned non-fluorinated underlying remainder layer of the partially fluorinated patterned photoresist layer. The reactive ion etch (RIE) plasma etch method also simultaneously forms upon the sidewalls of the via a metal-polymer residue layer. There is then removed, at least partially, the patterned fluorinated surface layer of the partially fluorinated patterned photoresist layer through a first stripping method employing an argon containing plasma under conditions such that the metal-polymer residue layer is not substantially oxidized. Finally, there is then removed through a second stripping method at least the metal-polymer residue layer from the sidewalls of the via.

摘要翻译： 一种用于从图案化的含硅电介质层去除用于图案化含硅介电层的图案化部分氟化的光致抗蚀剂层的方法。 首先在半导体衬底上形成具有在其上形成的含硅电介质层的金属接触层。 然后在含硅介电层上形成图案化的光致抗蚀剂层。 然后通过使用通过含硅介电层的含氟蚀刻剂通孔的反应离子蚀刻（RIE）等离子体蚀刻方法形成，以形成到达金属接触层的图案化的含硅介电层。 反应离子蚀刻（RIE）等离子体蚀刻方法同时从图案化的光致抗蚀剂层形成部分氟化的图案化光致抗蚀剂层，其包括部分氟化的图案化光致抗蚀剂层的图案化氟化表面层和部分氟化图案化的图案化的图案化的非氟化下面的剩余层 光致抗蚀剂层。 反应离子蚀刻（RIE）等离子体蚀刻方法也同时在通孔的侧壁上形成金属 - 聚合物残余层。 然后，在使得金属 - 聚合物残余层基本上不被氧化的条件下，通过使用含氩等离子体的第一剥离方法，至少部分地去除部分氟化的图案化光致抗蚀剂层的图案化氟化表面层。 最后，然后通过第二次剥离方法从通孔的侧壁至少去除金属 - 聚合物残余物层。

公开(公告)号：US20140054679A1

公开(公告)日：2014-02-27

申请号：US13592191

申请日：2012-08-22

申请人： Daniel TANG ,  Tzu-Shih YEN

发明人： Daniel TANG ,  Tzu-Shih YEN

IPC分类号： H01L29/78 ,  H01L21/84 ,  H01L21/336

CPC分类号： H01L29/66803 ,  H01L21/26586 ,  H01L21/823431 ,  H01L29/785

摘要： In doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. A first ion implant is performed in a region of the non-planar semiconductor body. The first ion implant has a first implant energy and a first implant angle. A second ion implant is performed in the same region of the non-planar semiconductor body. The second ion implant has a second implant energy and a second implant angle. The first implant energy may be different from the second implant energy. Additionally, the first implant angle may be different from the second implant angle.

摘要翻译： 在掺杂非平面半导体器件中，获得了在其上形成非平面半导体体的衬底。 在非平面半导体本体的区域中执行第一离子注入。 第一离子注入具有第一注入能量和第一注入角度。 在非平面半导体本体的相同区域中执行第二离子注入。 第二离子注入具有第二注入能量和第二注入角度。 第一注入能量可以不同于第二注入能量。 另外，第一植入角度可以不同于第二植入角度。

公开(公告)号：US20080123430A1

公开(公告)日：2008-05-29

申请号：US11476645

申请日：2006-06-29

申请人： Tzu-shih Yen

发明人： Tzu-shih Yen

IPC分类号： H01L29/68 ,  G11C11/34 ,  G11C7/00 ,  H01L29/788

CPC分类号： H01L29/7923 ,  G11C17/16 ,  H01L27/0207 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/1126 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A memory unit comprising a gate electrode, a gate dielectric under said gate electrode, an active area and a metal-semiconductor compound layer is provided. The active area comprises a first source/drain region, a second source/drain region, a normal field channel region formed under said gate electrode, a fringing field channel region formed between said first source/drain region and said normal field channel region, and an extension doping region formed between said second source/drain region and said normal field channel region. The metal-semiconductor compound layer is formed over said gate electrode, first source/drain region and second source/drain region.

摘要翻译： 一种存储单元，包括栅电极，所述栅电极下的栅极电介质，有源区和金属半导体化合物层。 有源区包括第一源极/漏极区域，第二源极/漏极区域，形成在所述栅极电极下方的正常场通道区域，形成在所述第一源极/漏极区域和所述正常场通道区域之间的边界场区域，以及 形成在所述第二源极/漏极区域和所述正常场通道区域之间的延伸掺杂区域。 金属 - 半导体化合物层形成在所述栅电极，第一源极/漏极区域和第二源极/漏极区域上。

公开(公告)号：US06376384B1

公开(公告)日：2002-04-23

申请号：US09557398

申请日：2000-04-24

申请人： Tzu-Shih Yen ,  Erik S. Jeng ,  I-Ping Lee ,  Eddy Chiang

发明人： Tzu-Shih Yen ,  Erik S. Jeng ,  I-Ping Lee ,  Eddy Chiang

IPC分类号： H01L21302

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76897 ,  Y10S438/963

摘要： A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and oxygen. The method may also be employed in general for etching silicon oxide layers in the presence of silicon nitride layers. Similarly, the method may also in general be employed in removing fluorocarbon polymer residue layers from integrated circuit layers including but not limited to silicon oxide layers and silicon nitride layers.

摘要翻译： 一种通过氧化硅层形成通孔的方法。 首先提供基板。 然后在衬底上形成图案化的氮化硅层，其限定图案化氮化硅层下面的接触区域。 然后在图案化的氮化硅层上形成氧化硅层。 然后在使用包含氟碳化合物蚀刻剂气体的第一蚀刻剂气体组合物的反应离子蚀刻（RIE）方法的同时蚀刻氧化硅层，以形成：（1）蚀刻的氧化硅层，其暴露接触区域而基本上不蚀刻图案 氮化硅层; 和（2）在蚀刻的氧化硅层和图案化氮化硅层中的至少一个上形成的氟碳聚合物残渣层。 最后，使用包含碳氟化合物蚀刻剂气体和氧气的第二蚀刻剂气体组合物的下游等离子体蚀刻方法，从基底上剥离碳氟聚合物残余物层。 该方法通常也可用于在存在氮化硅层的情况下蚀刻氧化硅层。 类似地，该方法通常也可用于从包括但不限于氧化硅层和氮化硅层的集成电路层去除碳氟聚合物残余物层。

公开(公告)号：US06235621B1

公开(公告)日：2001-05-22

申请号：US09447008

申请日：1999-11-22

申请人： Erik S. Jeng ,  Tzu-Shih Yen ,  Chi-San Wu ,  Jong-Bor Wang

发明人： Erik S. Jeng ,  Tzu-Shih Yen ,  Chi-San Wu ,  Jong-Bor Wang

IPC分类号： H01L213205

CPC分类号： H01L21/28114 ,  H01L21/28061 ,  H01L21/31111 ,  H01L21/76897 ,  H01L29/42376 ,  H01L29/6656

摘要： A method for fabricating semiconductor device is disclosed herein. The first step is to form a first oxide layer on a substrate. Subsequently formed are polycrystalline silicon layer, a polycide layer, optionally a second oxide layer, and a silicon nitride layer on the first oxide layer. A photoresist pattern on the silicon layer is formed thereafter, and the silicon nitride layer is etched using the photoresist pattern as a mask to expose a portion of the polycide layer. The photoresist pattern is then, the polycide layer is isotropically etched to form an under cut in the polycide layer under the etched nitride layer (optional second oxide layer). The width of the top portion of the isotropically etched polycide layer is smaller than the width of the etched nitride layer. The isotropically etched polycide layer is then anistropically etched, and the polycrystalline layer is etched to expose a portion of the first oxide layer to form a multi-layer structure. Finally, spacers on side-walls of the multi-layer structure are formed to create the semiconductor device, the side-wall of the anisotropicaly etched polycide layer generated after the oxidation process is prevented from penetrating the spacer of the semiconductor device according to the present invention.

摘要翻译： 本文公开了半导体器件的制造方法。 第一步是在衬底上形成第一氧化物层。 随后形成的是多晶硅层，多晶硅化物层，任选的第二氧化物层和第一氧化物层上的氮化硅层。 此后形成硅层上的光致抗蚀剂图案，并且使用光致抗蚀剂图案作为掩模蚀刻氮化硅层以暴露多晶硅化物层的一部分。 然后，光致抗蚀剂图案，多孔体层被各向同性地蚀刻以在蚀刻的氮化物层（可选的第二氧化物层）下的多晶硅化物层中形成下切割。 各向同性蚀刻的多晶硅化物层的顶部的宽度小于被蚀刻的氮化物层的宽度。 然后对各向同性蚀刻的多晶硅化物层进行水磨蚀蚀刻，并且蚀刻多晶层以暴露第一氧化物层的一部分以形成多层结构。 最后，形成多层结构的侧壁上的间隔物以形成半导体器件，防止在氧化处理之后产生的各向异性热蚀刻的多晶硅化物层的侧壁穿透根据本发明的半导体器件的间隔物 发明。