公开(公告)号：US20120195591A1

公开(公告)日：2012-08-02

申请号：US13444762

申请日：2012-04-11

申请人： Alan Benner ,  Ramakrishnan Rajamony ,  Eugen Schenfeld ,  Craig Brian Stunkel ,  Peter A. Walker

发明人： Alan Benner ,  Ramakrishnan Rajamony ,  Eugen Schenfeld ,  Craig Brian Stunkel ,  Peter A. Walker

IPC分类号： H04L12/66 ,  H04J14/00

CPC分类号： H04L12/4641 ,  H04L12/28 ,  H04L12/66

摘要： A computing system includes: a plurality of tightly coupled processing nodes; a plurality of circuit switched networks using a circuit switching mode, interconnecting the processing nodes, and handling data transfers that meet one or more criteria; and a plurality of electronic packet switched networks, also interconnecting the processing nodes, handling data transfers that do meet the at least one criteria. The circuit switched networks and the electronic packet switched networks operate simultaneously.

摘要翻译： 计算系统包括：多个紧密耦合的处理节点; 使用电路交换模式的多个电路交换网络，互连处理节点，以及处理满足一个或多个标准的数据传输; 以及多个电子分组交换网络，其还互连处理节点，处理满足至少一个准则的数据传输。 电路交换网络和电子分组交换网络同时工作。

公开(公告)号：US08230422B2

公开(公告)日：2012-07-24

申请号：US11034546

申请日：2005-01-13

申请人： Patrick Joseph Bohrer ,  Orran Yaakov Krieger ,  Ramakrishnan Rajamony ,  Michael Rosenfield ,  Hazim Shafi ,  Balaram Sinharoy ,  Robert Brett Tremaine

发明人： Patrick Joseph Bohrer ,  Orran Yaakov Krieger ,  Ramakrishnan Rajamony ,  Michael Rosenfield ,  Hazim Shafi ,  Balaram Sinharoy ,  Robert Brett Tremaine

IPC分类号： G06F9/46 ,  G06F9/40 ,  G06F13/28

CPC分类号： G06F9/383 ,  G06F9/3851 ,  G06F9/4881 ,  G06F12/0862

摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

摘要翻译： 数据处理系统包括具有访问多级缓存存储器的微处理器。 微处理器执行从源代码对象编译的主线程。 该系统包括用于执行也源自源代码对象的辅助线程的处理器。 辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。 配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。 辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

公开(公告)号：US08146094B2

公开(公告)日：2012-03-27

申请号：US12024678

申请日：2008-02-01

申请人： Lakshminarayana B. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  Hanhong Xue

发明人： Lakshminarayana B. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  Hanhong Xue

IPC分类号： G06F13/00 ,  G06F9/46 ,  G06F15/16 ,  H04J1/16 ,  H04B7/005 ,  H04B1/44

CPC分类号： H04L1/1642 ,  G06F9/542

摘要： A target task ensures complete delivery of a global shared memory (GSM) message from an originating task to the target task. The target task's HFI receives a first of multiple GSM packets generated from a single GSM message sent from the originating task. The HFI logic assigns a sequence number and corresponding tuple to track receipt of the complete GSM message. The sequence number is unique relative to other sequence numbers assigned to GSM messages that have not been completely received from the initiating task. The HFI updates a count value within the tuple, which comprises the sequence number and the count value for the first GSM packet and for each subsequent GSM packet received for the GSM message. The HFI determines when receipt of the GSM message is complete by comparing the count value with a count total retrieved from the packet header.

摘要翻译： 目标任务确保从始发任务到目标任务的全局共享存储器（GSM）消息的完全传递。 目标任务的HFI接收从发起任务发送的单个GSM消息产生的多个GSM分组中的第一个。 HFI逻辑分配序列号和对应的元组来跟踪完整GSM消息的接收。 相对于分配给尚未完全从发起任务接收的GSM消息的其他序列号，序列号是唯一的。 HFI更新元组内的计数值，其包括第一GSM分组的序列号和计数值以及为GSM消息接收的每个后续GSM分组。 通过将计数值与从分组报头检索的计数总数进行比较，HFI确定接收到GSM消息的完成。

公开(公告)号：US08140759B2

公开(公告)日：2012-03-20

申请号：US12424716

申请日：2009-04-16

申请人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

发明人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

IPC分类号： G06F13/00

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0817 ,  G06F2212/6028

摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.

摘要翻译： 用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。 处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。 访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。 响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

公开(公告)号：US08127300B2

公开(公告)日：2012-02-28

申请号：US11846119

申请日：2007-08-28

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  William E. Speight

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  William E. Speight

IPC分类号： G06F9/46 ,  G06F15/173

CPC分类号： G06F9/522 ,  G06F9/5083

摘要： Mechanisms for providing hardware based dynamic load balancing of message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.

摘要翻译： 提供了提供消息传递接口（MPI）任务的基于硬件的动态负载平衡的机制。 提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。 根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。 因此，可以执行操作以将工作负载从最慢的处理器转移到一个或多个更快的处理器。

公开(公告)号：US20110022773A1

公开(公告)日：2011-01-27

申请号：US12509752

申请日：2009-07-27

申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0864 ,  G06F12/126 ,  Y02D10/13

摘要： A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.

摘要翻译： 在虚拟机监视器中提供了用于共享高速缓存中的细粒度高速缓存分配的机制。 该机制将高速缓存标签分成最高有效位（MSB）部分和最低有效位（LSB）部分。 标签的MSB部分在一组中的高速缓存行之间共享。 标签的LSB部分是私有的，每个缓存行一个。 该机制允许软件将缓存中的标签的MSB部分设置为分配高速缓存行集合。 高速缓存控制器基于标签的MSB部分来确定高速缓存行是否被锁定。

公开(公告)号：US20100268886A1

公开(公告)日：2010-10-21

申请号：US12424716

申请日：2009-04-16

申请人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

发明人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0817 ,  G06F2212/6028

摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.

摘要翻译： 用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。 处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。 访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。 响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

公开(公告)号：US20090199046A1

公开(公告)日：2009-08-06

申请号：US12024585

申请日：2008-02-01

申请人： Lakshminarayana B. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  Hanhong Xue

发明人： Lakshminarayana B. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  Hanhong Xue

IPC分类号： G06F11/00

CPC分类号： G06F13/385

摘要： A host fabric interface (HFI) enables debugging of global shared memory (GSM) operations received at a local node from a network fabric. The local node has a memory management unit (MMU), which provides an effective address to real address (EA-to-RA) translation table that is utilized by the HFI to evaluate when EAs of GSM operations/data from a received GSM packet is memory-mapped to RAs of the local memory. The HFI retrieves the EA associated with a GSM operation/data within a received GSM packet. The HFI forwards the EA to the MMU, which determines when the EA is mapped to RAs within the local memory for the local task. The HFI processing logic enables processing of the GSM packet only when the EA of the GSM operation/data within the GSM packet is an EA that has a local RA translation. Non-matching EAs result in an error condition that requires debugging.

摘要翻译： 主机结构接口（HFI）可以调试从网络结构在本地节点接收到的全局共享存储器（GSM）操作。 本地节点具有存储器管理单元（MMU），该存储器管理单元（MMU）为HFI用于实际地址（EA-to-RA）转换表提供有效地址，以评估来自接收到的GSM分组的GSM操作/数据的EAs是否为 内存映射到本地内存的RA。 HFI检索与接收的GSM分组内的GSM操作/数据相关联的EA。 HFI将EA转发到MMU，该MMU确定EA何时映射到本地内存中的本地任务的RA。 HFI处理逻辑仅当GSM操作的EA / GSM分组内的数据是具有本地RA转换的EA时才能处理GSM分组。 不匹配的EA会导致需要调试的错误条件。

公开(公告)号：US20090198918A1

公开(公告)日：2009-08-06

申请号：US12024397

申请日：2008-02-01

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  William J. Starke ,  Hanhong Xue

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  William J. Starke ,  Hanhong Xue

IPC分类号： G06F12/02

CPC分类号： G06F12/109 ,  G06F9/544

摘要： A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping.

摘要翻译： 数据处理系统通过物理内存的分布式EA-to-RA映射实现跨多个节点的全局共享存储（GSM）操作。 每个节点都有一个主机结构接口（HFI），它包括分配给并行作业最多一个本地执行任务的HFI窗口。 任务执行并行作业执行，但将全局地址空间的有效地址（EA）的一部分映射到任务相应节点的本地实际存储器。 HFI窗口使用作业ID对所有传出的GSM操作（本地任务）进行标记，并嵌入EA被映射到的节点的目标节点和HFI窗口ID。 HFI窗口还能够利用归属于接收节点的本地实际存储器的有效EA来处理接收的GSM操作，同时防止在没有有效的EA到RA本地映射的情况下处理其他接收到的操作。

公开(公告)号：US20090198891A1

公开(公告)日：2009-08-06

申请号：US12024437

申请日：2008-02-01

申请人： Lakshimarayana B. Arimilli ,  Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  William J. Starke ,  Hanhong Xue

发明人： Lakshimarayana B. Arimilli ,  Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  William J. Starke ,  Hanhong Xue

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0815 ,  G06F12/0897 ,  G06F12/10

摘要： A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping.

摘要翻译： 数据处理系统通过物理内存的分布式EA-to-RA映射实现跨多个节点的全局共享存储（GSM）操作。 每个节点都有一个主机结构接口（HFI），它包括分配给并行作业最多一个本地执行任务的HFI窗口。 任务执行并行作业执行，但将全局地址空间的有效地址（EA）的一部分映射到任务相应节点的本地实际存储器。 HFI窗口使用作业ID对所有传出的GSM操作（本地任务）进行标记，并嵌入EA被映射到的节点的目标节点和HFI窗口ID。 HFI窗口还能够利用归属于接收节点的本地实际存储器的有效EA来处理接收的GSM操作，同时防止在没有有效的EA到RA本地映射的情况下处理其他接收到的操作。