公开(公告)号：US08140759B2

公开(公告)日：2012-03-20

申请号：US12424716

申请日：2009-04-16

申请人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

发明人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

IPC分类号： G06F13/00

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0817 ,  G06F2212/6028

摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.

摘要翻译： 用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。 处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。 访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。 响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

公开(公告)号：US20100268886A1

公开(公告)日：2010-10-21

申请号：US12424716

申请日：2009-04-16

申请人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

发明人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0817 ,  G06F2212/6028

摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.

摘要翻译： 用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。 处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。 访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。 响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

公开(公告)号：US06338119B1

公开(公告)日：2002-01-08

申请号：US09282631

申请日：1999-03-31

申请人： Gary Dean Anderson ,  Ronald Xavier Arroyo ,  Bradly George Frey ,  Guy Lynn Guthrie

发明人： Gary Dean Anderson ,  Ronald Xavier Arroyo ,  Bradly George Frey ,  Guy Lynn Guthrie

IPC分类号： G06F1300

CPC分类号： G06F12/0835 ,  G06F13/28

摘要： A method and apparatus for improving direct memory access and cache performance utilizing a special Input/Output or “I/O” page, defined as having a large size (e.g., 4 Kilobytes or 4 Kb), but with distinctive cache line characteristics. For Direct Memory Access (DMA) reads, the first cache line in the I/O page may be accessed, by a Peripheral Component Interconnect (PCI) Host Bridge, as a cacheable read and all other lines are non-cacheable access (DMA Read with no intent to cache). For DMA writes, the PCI Host Bridge accesses all cache lines as cacheable. The PCI Host Bridge maintains a cache snoop granularity of the I/O page size for data, which means that if the Host Bridge detects a store (invalidate) type system bus operation on any cache line within an I/O page, cached data within that page is invalidated, the Level 1 and Level 2 ((L1/L2) caches continue to treat all cache lines in this page as cacheable). By defining the first line as cacheable, only one cache line need be invalidated on the system bus by the L1/L2 cache in order to cause invalidation of the whole page of data in the PCI Host Bridge. All stores to the other cache lines in the I/O Page can occur directly in the L1/L2 cache without system bus operations, since these lines have been left in the ‘modified’ state in the L1/L2 cache.

摘要翻译： 使用定义为具有大尺寸（例如4千字节或4Kb）但具有鲜明的高速缓存行特征的特殊输入/输出或“I / O”页来改善直接存储器访问和高速缓存性能的方法和装置。 对于直接存储器访问（DMA）读取，I / O页面中的第一个高速缓存行可以由外围组件互连（PCI）主机桥访问，作为可缓存读取，并且所有其他行都是非高速缓存访​​问（DMA读取 没有意图缓存）。 对于DMA写操作，PCI主机桥可以将所有缓存行访问为可缓存的。 PCI主机桥保持数据的I / O页面大小的缓存窥探粒度，这意味着如果主机桥检测到I / O页面中的任何缓存行上的存储（无效）类型的系统总线操作，则缓存数据 该页面无效，级别1和级别2（（L1 / L2）高速缓存继续将该页面中的所有高速缓存行视为可缓存）。 通过将第一行定义为可缓存的，L1 / L2缓存只能在系统总线上只有一条高速缓存行无效，从而导致PCI主机桥中整个数据页的无效。 所有存储到I / O页面中的其他高速缓存行的存储可以直接发生在L1 / L2高速缓存中，而不需要系统总线操作，因为这些行在L1 / L2缓存中保持“修改”状态。

公开(公告)号：US07350029B2

公开(公告)日：2008-03-25

申请号：US11054889

申请日：2005-02-10

申请人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

发明人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

摘要翻译： 在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。 数据预取请求被分配与数据流以反映确定的数据流的深度。 分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。 该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。 由处理器执行的指令中的预取控制位控制预取硬件配置。

公开(公告)号：US07904661B2

公开(公告)日：2011-03-08

申请号：US11953637

申请日：2007-12-10

申请人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

发明人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

摘要翻译： 在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。 数据预取请求被分配与数据流以反映确定的数据流的深度。 分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。 该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。 由处理器执行的指令中的预取控制位控制预取硬件配置。

公开(公告)号：US20120284465A1

公开(公告)日：2012-11-08

申请号：US13549898

申请日：2012-07-16

申请人： Bradly George Frey ,  Michal Ostrowski ,  Andrew Henry Wottreng

发明人： Bradly George Frey ,  Michal Ostrowski ,  Andrew Henry Wottreng

IPC分类号： G06F12/06 ,  G06F12/00

CPC分类号： G06F9/45558 ,  G06F2009/45583

摘要： An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.

公开(公告)号：US08589657B2

公开(公告)日：2013-11-19

申请号：US12983989

申请日：2011-01-04

申请人： Bradly George Frey ,  Michal Ostrowski ,  Andrew Henry Wottreng

发明人： Bradly George Frey ,  Michal Ostrowski ,  Andrew Henry Wottreng

IPC分类号： G06F12/00

CPC分类号： G06F9/45558 ,  G06F2009/45583

摘要： An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.

摘要翻译： 在超级计算机系统中提供了一种方法，其中页表请求处于在超监督计算机系统中运行的操作系统。 操作系统确定页表请求是否要求管理程序处理。 如果确定显示页表请求需要管理程序，则使用管理程序来处理该请求。 然而，如果确定显示页表请求不需要管理程序，则读取包含在与该请求对应的页表项中的指示符，以确定页表项是否由操作系统或管理程序控制。 如果指示符将页表条目标识为操作系统控制，则操作系统能够更新页表条目。

公开(公告)号：US20120173842A1

公开(公告)日：2012-07-05

申请号：US12983989

申请日：2011-01-04

申请人： Bradly George Frey ,  Michal Ostrowski ,  Andrew Henry Wottreng

发明人： Bradly George Frey ,  Michal Ostrowski ,  Andrew Henry Wottreng

IPC分类号： G06F12/10

CPC分类号： G06F9/45558 ,  G06F2009/45583

摘要： An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.

摘要翻译： 在超级计算机系统中提供了一种方法，其中页表请求处于在超监督计算机系统中运行的操作系统。 操作系统确定页表请求是否要求管理程序处理。 如果确定显示页表请求需要管理程序，则使用管理程序来处理该请求。 然而，如果确定显示页表请求不需要管理程序，则读取包含在与该请求对应的页表项中的指示符，以确定页表项是否由操作系统或管理程序控制。 如果指示符将页表条目标识为操作系统控制，则操作系统能够更新页表条目。

公开(公告)号：US20080307190A1

公开(公告)日：2008-12-11

申请号：US11759685

申请日：2007-06-07

申请人： Richard Louis Arndt ,  Bradly George Frey

发明人： Richard Louis Arndt ,  Bradly George Frey

IPC分类号： G06F12/00

CPC分类号： G06F12/08 ,  G06F2212/1016 ,  G06F2212/151

摘要： A method for providing virtual real memory includes receiving a request for a memory page from a requestor. A system determines whether the requested memory page is available. In the event the requested memory page is available, the system satisfies the request. In the event the requested memory page is not available, the system generates a page fault interrupt, wherein the page fault interrupt comprises a first page fault correlation number (PFCID) identifying a restorative process, and wherein the restorative process is configured to restore the requested memory page to available memory. The system monitors a plurality of pending processes and determines whether the restorative process is complete. In the event the restorative process is complete, the system notifies the requester that the restorative process is complete.

摘要翻译： 一种用于提供虚拟真实存储器的方法包括从请求者接收对存储器页面的请求。 系统确定所请求的存储器页面是否可用。 在请求的内存页面可用的情况下，系统满足请求。 在所请求的存储器页面不可用的情况下，系统产生页面错误中断，其中页面错误中断包括识别修复过程的第一页面故障相关数（PFCID），并且其中修复过程被配置为恢复所请求的 内存页面到可用内存。 系统监视多个未决进程，并确定修复过程是否完成。 在修复过程完成的情况下，系统通知请求者修复过程已完成。

公开(公告)号：US5835738A

公开(公告)日：1998-11-10

申请号：US668530

申请日：1996-06-24

申请人： John Wiley Blackledge, Jr. ,  Bechara Boury ,  Bradly George Frey ,  James D. Reid ,  Ronald Valli

发明人： John Wiley Blackledge, Jr. ,  Bechara Boury ,  Bradly George Frey ,  James D. Reid ,  Ronald Valli

IPC分类号： G06F13/36 ,  G06F13/40 ,  H04L12/46 ,  H04L29/12 ,  G06F13/00

CPC分类号： H04L61/00 ,  G06F13/404 ,  H04L12/46 ,  H04L29/12009

摘要： An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.

摘要翻译： 信息处理系统包括处理器，用于根据不支持I / O地址信号的第一总线协议进行信号的第一总线; 用于根据支持输入/输出（I / O）地址信号的第二总线协议进行信号的第二总线; 以及用于将第一总线耦合到第二总线的桥接电路。 处理器包括用于发射地址信号的电路和指向所选外围设备的地址类型信号。 桥接电路包括一个滤波器，用于确定由处理器发出的地址信号是否对应于耦合到从属于该桥接电路的总线的外围设备; 以及耦合到所述滤波器的翻译电路，用于将根据所述第一总线协议的信号转换为根据所述第二总线协议的信号以传输到所选择的外围设备。