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公开(公告)号：US5982692A
公开(公告)日：1999-11-09
申请号：US905000
申请日：1997-08-01
CPC分类号： G11C7/18 , G11C7/1048 , G11C7/12
摘要： A method and apparatus is provided for implementing a memory cell array having a performance-improved critical read path using a boost amplifier configuration. The memory bit line is broken into small segments with a boost amplifier and the bit line is connected to the input of the amplifier. The output of the amplifier drives the global bit line. The amplifier is turned "on" during a "read" and turned "off" during a "write". During a read, one memory cell within one array segment is turned on. The memory cell drives the differential signal on to the local bit line pair. Also during a read, the boost amplifier which attaches to that local bit line is enabled. The boost amplifier amplifies the input signal (local bit line pair) and drives that signal on to the global bit line. Since the bit line is broken into small segments with boost amplifiers, there are many boost amplifiers attached on the global bit line. When enough signal is developed on the global bit line pair, the global sense amplifier is turned on. The bit line is thus quickly pulled to ground thereby significantly improving performance for the critical read path.
摘要翻译： 提供了一种用于实现具有使用升压放大器配置的性能改善的关键读取路径的存储单元阵列的方法和装置。 存储器位线用升压放大器分成小段，位线连接到放大器的输入。 放大器的输出驱动全局位线。 在“读取”期间，放大器“打开”并在“写入”期间关闭。 在读取期间，一个数组段内的一个存储单元被导通。 存储单元将差分信号驱动到本地位线对上。 此外，在读取期间，启用与本地位线相连的升压放大器。 升压放大器放大输入信号（局部位线对）并将该信号驱动到全局位线。 由于利用升压放大器将位线分解成小段，所以在全局位线上附加了许多升压放大器。 当在全局位线对上产生足够的信号时，全局读出放大器被打开。 因此，位线被快速拉到地，从而显着提高关键读路径的性能。
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公开(公告)号：US5877976A
公开(公告)日：1999-03-02
申请号：US959478
申请日：1997-10-28
摘要： An improved topology for multi-port memory cell layouts in which two or more bitline pairs are required for data transfers is provided. Bitlines are displaced vertically, rather than horizontally. Such vertical spacing provides improved silicon density while reducing bitline capacitance of a memory cell. Additionally, the use of vertically separated bitline pairs allows traditional transitional phase relationships between multi-port operations in multi-port memory implementations. To nullify any sensitivity to an overlapping restore operation, this improved topology includes cross-coupled ports.
摘要翻译： 提供了一种用于多端口存储器单元布局的改进的拓扑，其中需要两个或更多位线对来进行数据传输。 位线垂直位移，而不是水平位移。 这种垂直间隔提供了改进的硅密度，同时降低了存储单元的位线电容。 另外，使用垂直分离的位线对允许在多端口存储器实现中的多端口操作之间的传统的过渡相位关系。 为了消除对重复恢复操作的任何敏感性，该改进的拓扑包括交叉耦合端口。
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公开(公告)号：US5831896A
公开(公告)日：1998-11-03
申请号：US767772
申请日：1996-12-17
IPC分类号： G11C11/412 , G11C11/00
CPC分类号： G11C11/412
摘要： A five transistor memory cell, is a single ended static random access memory (SRAM) cell. Reading and writing from the cell is implemented with one bit line along with word line read and word line write signals. One of the transistors within the memory cell is not coupled directly to ground, but is instead coupled to a controlled impedance node. This permits the affected transistor to float between ground and a high impedance state, which permits one bit line to write into the memory cell.
摘要翻译： 一个五晶体管存储单元，是单端静态随机存取存储器（SRAM）单元。 从单元读取和写入通过一条位线以及字线读取和字线写入信号来实现。 存储单元内的晶体管之一不直接耦合到地，而是耦合到受控阻抗节点。 这允许受影响的晶体管在地之间浮动和高阻抗状态，这允许一个位线写入存储单元。
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公开(公告)号：US5694362A
公开(公告)日：1997-12-02
申请号：US668880
申请日：1996-06-24
摘要： According to the present invention, a comparison circuit for combining a plurality of data bits is provided. One version of the invention includes a comparator which provides a signal responsive to a comparison of the voltage states of at least two of the plurality of data bits, and an amplifier which is coupled to the comparator and compares the signal provided by the comparator to a reference voltage to provide an output signal, the reference voltage being between a high and a low voltage state.
摘要翻译： 根据本发明，提供了用于组合多个数据位的比较电路。 本发明的一个方案包括比较器，其提供响应于多个数据位中的至少两个的电压状态的比较的信号，以及耦合到比较器的放大器，并将比较器提供的信号与 参考电压以提供输出信号，参考电压处于高电压和低电压状态之间。
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25.发明授权Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing 失效数据处理系统包括具有真实地址标签阵列的加载/存储单元以及用于校正有效地址混叠的方法公开(公告)号：US06477635B1
公开(公告)日：2002-11-05
申请号：US09435862
申请日：1999-11-08
IPC分类号： G06F1210
CPC分类号： G06F12/1063 , G06F12/0831 , G06F12/0897
摘要： A data processing system including a processor having a load/store unit and a method for correcting effective address aliasing. In the load/store unit within the processor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. A real address tag is utilized to correct for effective address aliasing within the load/store unit.
摘要翻译： 一种数据处理系统，包括具有加载/存储单元的处理器和用于校正有效地址混叠的方法。 在处理器内的加载/存储单元中，加载和存储指令按顺序执行。 加载和存储指令以预定方式分配标签，然后分配给加载和存储重新排序队列，以跟踪加载和存储指令的程序顺序。 利用真实地址标签来校正加载/存储单元内的有效地址混叠。
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26.发明授权Memory system having a unidirectional bus and method for communicating therewith 失效具有单向总线的存储器系统和与其通信的方法公开(公告)号：US06195280B1
公开(公告)日：2001-02-27
申请号：US09521352
申请日：2000-03-09
IPC分类号： G11C506
CPC分类号： G11C7/1048 , G11C7/12 , G11C7/18
摘要： A memory and a method for communicating therewith are implemented having a unidirectional write bus for writing to memory cells within a plurality of memory cell groups. Local bitlines associated with each of the memory cell groups communicate write data to the associated memory cell. Global bitlines coupled to all of the memory cells are decoupled from the local bitlines during a write operation. Following a write operation the local bitlines are restored by a precharge operation during which the global and local bitlines are also decoupled.
摘要翻译： 实现了与其通信的存储器和方法，其具有用于写入多个存储单元组内的存储单元的单向写总线。 与每个存储器单元组相关联的本地位线将写入数据传送到相关联的存储器单元。 耦合到所有存储器单元的全局位线在写操作期间与本地位线分离。 在写操作之后，通过预充电操作来恢复局部位线，在此期间，全局和本地位线也被去耦。
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公开(公告)号：US6157216A
公开(公告)日：2000-12-05
申请号：US296875
申请日：1999-04-22
IPC分类号： G11C11/418 , G11C11/407 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/786 , H03K19/003 , H03K19/017 , H03K19/0175
CPC分类号： H03K19/01707
摘要： A silicon-on-insulator digital circuit combination having a body voltage control stage and a voltage clamp stage. The body voltage control stage is responsive to an input control signal to provide an output driver signal. The body voltage control stage has a first transistor with a terminal for electrically-coupling to a combinational logic circuit, and a body contact electrically-coupled to the input control signal such that a threshold voltage of the transistor is reduced when the transistor is placed in an active state. It can be readily appreciated that the reduced threshold voltage of the transistor increases the transition rate for the first transistor to an inactive state in response to the input control signal. The voltage clamp stage has a second transistor responsive to the input control signal such that the terminal is electrically-coupled to a reference voltage when the first transistor is in the inactive state.
摘要翻译： 一种具有体电压控制级和电压钳位级的绝缘体上硅数字电路组合。 体电压控制级响应于输入控制信号以提供输出驱动器信号。 体电压控制级具有第一晶体管，其具有用于电耦合到组合逻辑电路的端子和与输入控制信号电耦合的体接触，使得当晶体管放置在晶体管时晶体管的阈值电压降低 活跃状态。 可以容易地理解，晶体管的降低的阈值电压响应于输入控制信号将第一晶体管的转变速率增加到无效状态。 电压钳位级具有响应于输入控制信号的第二晶体管，使得当第一晶体管处于非活动状态时，端子与参考电压电耦合。
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公开(公告)号：US6144609A
公开(公告)日：2000-11-07
申请号：US361363
申请日：1999-07-26
CPC分类号： G11C8/16
摘要： A multiport memory cell having a reduced number of write wordlines is disclosed. The multiport memory cell capable of simultaneously reading data from and writing data to a storage cell comprises a storage cell for storing data, a decoder, write wordlines, write bitlines, read wordlines, and read bitlines. The write wordlines and the write bitlines are utilized to input write data into the storage cell. The read wordlines and the read bitlines are utilized to output data from the storage cell. The write bitlines are directly coupled to the storage cell, and some or all of the write wordlines are coupled to the storage cell via the decoder for the purpose of wire reduction. Similar to the write bitlines, all the read bitlines and read wordlines are directly coupled to the storage cell.
摘要翻译： 公开了具有减少数量的写字线的多端口存储单元。 能够同时从存储单元读取数据并将数据写入存储单元的多端口存储单元包括用于存储数据的存储单元，解码器，写字线，写位线，读字线和读位线。 写入字线和写位线用于将写入数据输入存储单元。 读取字线和读位线用于从存储单元输出数据。 写入位线直接耦合到存储单元，并且为了减少线的目的，部分或全部写入字线通过解码器耦合到存储单元。 与写入位线类似，所有读取的位线和读取字线都直接耦合到存储单元。
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29.发明授权Conditional restore for RAM based on feedback from a RAM cell to precharge circuitry 失效基于从RAM单元到预充电电路的反馈来对RAM进行条件恢复
公开(公告)号：US6108255A
公开(公告)日：2000-08-22
申请号：US128017
申请日：1998-07-30
IPC分类号： G11C11/41 , G11C7/12 , G11C7/22 , G11C11/417 , G11C11/419 , G06F12/16
CPC分类号： G11C7/12 , G11C11/417 , G11C11/419 , G11C7/22
摘要： A novel SRAM construction allows for reduced power consumption by conditionally restoring only those memory cells which are evaluated (subjected to a read or write operation). The device includes a memory array containing an arbitrary number of memory cells, a plurality of word lines, and a plurality of predecoded address lines which allow selection of one of said word lines, wherein the memory cells are arranged in groups, each group having a bit line connected thereto. A precharge circuit is connected to the bit lines, and restores a given one of the memory cells after the evaluation operation. The predecoded address lines carry encoded information regarding an address associated with the evaluated memory cell, and a decoder identifies the address to determine which of the word lines should be used to access the evaluated cell. In one embodiment, the precharge circuit is responsive to control logic associated with the address (and carried on the predecoded address lines). In an alternative embodiment, a conditional restore circuit is used which selects the bit line based on data fed back to the precharge circuit from the output of the evaluated memory cell.
摘要翻译： 一种新颖的SRAM结构允许通过有条件地恢复被评估（经过读或写操作）的那些存储单元来降低功耗。 该装置包括存储阵列，该存储器阵列包含任意数量的存储单元，多条字线以及允许选择所述字线之一的多个预解码地址线，其中存储单元被分组布置，每组具有 与其连接的位线。 预充电电路连接到位线，并且在评估操作之后恢复给定的一个存储单元。 预解码地址线携带关于与所评估的存储器单元相关联的地址的编码信息，并且解码器识别地址以确定应当使用哪个字线来访问所评估的单元。 在一个实施例中，预充电电路响应于与地址相关联的控制逻辑（并且在预解码地址线上承载）。 在替代实施例中，使用条件恢复电路，其基于从所评估的存储器单元的输出反馈到预充电电路的数据来选择位线。
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公开(公告)号：US6046930A
公开(公告)日：2000-04-04
申请号：US144871
申请日：1998-09-01
IPC分类号： G11C8/16 , G11C11/412 , G11C11/419 , G11C11/00
CPC分类号： G11C11/419 , G11C11/412 , G11C8/16
摘要： A column (10) of a memory array includes a plurality of memory cells (11, 12) each having first and second independent access ports (T1, T2) and a cross-coupled memory latch (20). The first access port (T1) of each memory cell (11, 12) connects a first node (21) of the latch (20) to a first bit line (14), while the second access port (T2) of each memory cell connects a second node (22) of the latch (20) to a second bit line (15). A clearing arrangement (T7) is connected to the second bit line (15) for selectively coupling the second bit line to ground. A write driver is connected to the first bit line (14) for writing data to the memory cells (11, 12) in the form of single-ended signals. A memory cell is placed in a preset condition by simultaneously coupling the second node (22) to the second bit line (15) through the second access port (T2) and coupling the second bit line to ground through the clearing arrangement (T7). Once in the preset condition, data may be written to the cell by coupling the first bit line (14) to the first node (21) through the first access port (T1) and driving data to the first bit line.
摘要翻译： 存储器阵列的列（10）包括多个具有第一和第二独立访问端口（T1，T2）和交叉耦合存储器锁存器（20）的存储器单元（11,12）。 每个存储单元（11,12）的第一访问端口（T1）将锁存器（20）的第一节点（21）连接到第一位线（14），而每个存储单元的第二访问端口（T2） 将锁存器（20）的第二节点（22）连接到第二位线（15）。 清除装置（T7）连接到第二位线（15），用于选择性地将第二位线耦合到地。 写驱动器连接到第一位线（14），用于以单端信号的形式将数据写入存储单元（11,12）。 通过同时通过第二访问端口（T2）将第二节点（22）耦合到第二位线（15）并通过清除装置（T7）将第二位线耦合到地，将存储器单元置于预设状态。 一旦处于预设状态，通过将第一位线（14）通过第一访问端口（T1）耦合到第一节点（21）并将数据驱动到第一位线，可以将数据写入单元。
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