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公开(公告)号：US6064616A
公开(公告)日：2000-05-16
申请号：US128018
申请日：1998-07-30
IPC分类号： G11C11/41 , G11C7/12 , G11C7/22 , G11C11/417 , G11C11/419 , G11C11/401
CPC分类号： G11C7/12 , G11C11/417 , G11C11/419 , G11C7/22
摘要： A novel SRAM construction allows for reduced power consumption by conditionally restoring only these memory cells which are evaluated (subjected to a read or write operation). The device includes a memory array containing an arbitrary number of memory cells, a plurality of word lines, and a plurality of predecoded address lines which allow selection of one of said word lines, wherein the memory cells are arranged in groups, each group having a bit line connected thereto. A precharge circuit is connected to the bit lines, and restores a given one of the memory cells after the evaluation operation. The predecoded address lines carry encoded information regarding an address associated with the evaluated memory cell, and a decoder identifies the address to determine which of the word lines should be used to access the evaluated cell. In one embodiment, the precharge circuit is responsive to control logic associated with the address (and carried on the predecoded address lines). In an alternative embodiment, a conditional restore circuit is used which selects the bit line based on data fed back to the precharge circuit from the output of the evaluated memory cell.
摘要翻译： 一种新颖的SRAM结构允许通过有条件地恢复被评估（经过读或写操作）的这些存储器单元来降低功耗。 该装置包括存储阵列，该存储器阵列包含任意数量的存储单元，多条字线以及允许选择所述字线之一的多个预解码地址线，其中存储单元被分组布置，每组具有 与其连接的位线。 预充电电路连接到位线，并且在评估操作之后恢复给定的一个存储单元。 预解码地址线携带关于与所评估的存储器单元相关联的地址的编码信息，并且解码器识别地址以确定应当使用哪个字线来访问所评估的单元。 在一个实施例中，预充电电路响应于与地址相关联的控制逻辑（并且在预解码地址线上承载）。 在替代实施例中，使用条件恢复电路，其基于从所评估的存储器单元的输出反馈到预充电电路的数据来选择位线。
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公开(公告)号：US6025741A
公开(公告)日：2000-02-15
申请号：US772643
申请日：1996-12-23
IPC分类号： G11C7/12 , G11C11/419 , H03K19/00
CPC分类号： G11C7/12 , G11C11/419
摘要： A circuit for conditionally restoring an execution unit in a computer processor, to reduce power consumption. Execution units, such as an arithmetic logic unit, shift/rotate unit, multiply unit, etc., have bits in transit that flow through a series of logic gates. These gates must be precharged after an operation has occurred to prepare the unit for the next operation. The conditional restore circuit evaluates either the data input to the execution unit, or the data output from the execution unit, to determine whether an operation has occurred. The precharge device for the execution is turned on only when the evaluation indicates that an operation has just occurred. The circuit includes an AND gate whose output controls the precharge device, and whose inputs include one line from the evaluation circuit, and one line for cycling (the system clock). In an embodiment wherein the execution unit has two operand multiplexers which receive the data input, the evaluation circuit includes two select line respectively connected to the multiplexers, and to inputs of the AND gate. In an alternative embodiment wherein the execution unit has data output in the form of a TRUE line and a COMPLEMENTARY line, the evaluation circuit includes a NOR gate means having a first input connected to said TRUE line, a second input connected to said COMPLEMENTARY line, and an output connected to said first input of the AND gate.
摘要翻译： 用于有条件地还原计算机处理器中的执行单元的电路，以减少功耗。 诸如算术逻辑单元，移位/旋转单元，乘法单元等的执行单元具有流经一系列逻辑门的传送位。 这些门必须在操作发生后进行预充电，以准备下一个操作的单元。 条件恢复电路评估输入到执行单元的数据或从执行单元输出的数据，以确定是否发生操作。 仅当评估指示刚刚发生操作时才执行用于执行的预充电装置。 该电路包括一个与门，其输出控制预充电装置，其输入包括来自评估电路的一条线和一条循环线（系统时钟）。 在其中执行单元具有接收数据输入的两个操作数复用器的实施例中，评估电路包括分别连接到多路复用器的两个选择线以及与门的输入。 在其中执行单元具有以TRUE线和COMPLEMENTARY线的形式的数据输出的替代实施例中，评估电路包括NOR门装置，其具有连接到所述TRUE线的第一输入端，连接到所述补充线路的第二输入端， 以及连接到与门的所述第一输入的输出。
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3.发明授权
公开(公告)号：US5706237A
公开(公告)日：1998-01-06
申请号：US729823
申请日：1996-10-08
IPC分类号： G11C7/10 , G11C7/12 , G11C11/412 , G11C11/419 , G11C29/04 , G11C11/401
CPC分类号： G11C7/1048 , G11C11/4125 , G11C11/419 , G11C29/04 , G11C7/12
摘要： An improved self-restore circuit and method for restoring the output line of a dynamic logic circuit. The self-restore circuit includes two transistors connected in series between the output line and the reference voltage node. The first transistor activates after an evaluation of the output line, while the second transistor only activates subsequent to the activation of the first transistor and the completion of an evaluation cycle. The self-restore circuit reduces the power consumption and safeguards against any soft error hits, wherein the second transistor protects against any soft error hits by actively pulling up the output line to the appropriate voltage.
摘要翻译： 一种用于恢复动态逻辑电路的输出线的改进的自恢复电路和方法。 自恢复电路包括串联连接在输出线和参考电压节点之间的两个晶体管。 第一晶体管在输出线的评估之后激活，而第二晶体管仅在第一晶体管的激活和评估周期的完成之后激活。 自恢复电路降低功耗并防止任何软错误命中，其中第二晶体管通过主动地将输出线提升到适当的电压来防止任何软错误命中。
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4.发明授权Conditional restore for RAM based on feedback from a RAM cell to precharge circuitry 失效基于从RAM单元到预充电电路的反馈来对RAM进行条件恢复
公开(公告)号：US6108255A
公开(公告)日：2000-08-22
申请号：US128017
申请日：1998-07-30
IPC分类号： G11C11/41 , G11C7/12 , G11C7/22 , G11C11/417 , G11C11/419 , G06F12/16
CPC分类号： G11C7/12 , G11C11/417 , G11C11/419 , G11C7/22
摘要： A novel SRAM construction allows for reduced power consumption by conditionally restoring only those memory cells which are evaluated (subjected to a read or write operation). The device includes a memory array containing an arbitrary number of memory cells, a plurality of word lines, and a plurality of predecoded address lines which allow selection of one of said word lines, wherein the memory cells are arranged in groups, each group having a bit line connected thereto. A precharge circuit is connected to the bit lines, and restores a given one of the memory cells after the evaluation operation. The predecoded address lines carry encoded information regarding an address associated with the evaluated memory cell, and a decoder identifies the address to determine which of the word lines should be used to access the evaluated cell. In one embodiment, the precharge circuit is responsive to control logic associated with the address (and carried on the predecoded address lines). In an alternative embodiment, a conditional restore circuit is used which selects the bit line based on data fed back to the precharge circuit from the output of the evaluated memory cell.
摘要翻译： 一种新颖的SRAM结构允许通过有条件地恢复被评估（经过读或写操作）的那些存储单元来降低功耗。 该装置包括存储阵列，该存储器阵列包含任意数量的存储单元，多条字线以及允许选择所述字线之一的多个预解码地址线，其中存储单元被分组布置，每组具有 与其连接的位线。 预充电电路连接到位线，并且在评估操作之后恢复给定的一个存储单元。 预解码地址线携带关于与所评估的存储器单元相关联的地址的编码信息，并且解码器识别地址以确定应当使用哪个字线来访问所评估的单元。 在一个实施例中，预充电电路响应于与地址相关联的控制逻辑（并且在预解码地址线上承载）。 在替代实施例中，使用条件恢复电路，其基于从所评估的存储器单元的输出反馈到预充电电路的数据来选择位线。
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公开(公告)号：US5953745A
公开(公告)日：1999-09-14
申请号：US758073
申请日：1996-11-27
CPC分类号： G11C29/78 , G06F12/0802 , G11C29/846
摘要： A set associative cache memory array includes redundant memory portions for use in the case of a defective portion of the memory. Information is stored within the defective portion of the memory array and an identical copy is stored within the redundant portion. Additionally, reading of the information is done from both the defective portion and the redundant portion. Selection of the information from either the defective portion or the redundant portion is made using programmable circuitry such as a fuse.
摘要翻译： 一组关联高速缓存存储器阵列包括用于在存储器的缺陷部分的情况下使用的冗余存储器部分。 信息存储在存储器阵列的缺陷部分内，并且相同的拷贝存储在冗余部分内。 此外，从缺陷部分和冗余部分两者进行信息的读取。 使用诸如保险丝的可编程电路来从缺陷部分或冗余部分中选择信息。
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公开(公告)号：US06243776B1
公开(公告)日：2001-06-05
申请号：US09114116
申请日：1998-07-13
IPC分类号： G06F1300
CPC分类号： G06F13/4072
摘要： A bus may be configured as either a single-ended mode bus or as a differential mode bus, depending on the system environment. The bus is configured in such a way that additional lines are not required, and so that substantially the same circuitry may be used for either single-ended mode or differential mode. Further, a selectable-mode driver may be connected to a non-selectable mode receiver, and vice versa. The invention may be implemented as a selectable driver, a selectable receiver, or a selectable driver/receiver pair. The apparatus and method of the present invention apply to both uni-directional and bi-directional bus implementations. The invention uses the same bus lines (i.e. wires) and substantially the same circuitry for both single-ended and differential modes of operation. When operating in single-ended mode, the data width of the bus is twice the data width as when operating in differential mode.
摘要翻译： 根据系统环境，总线可以配置为单端模式总线或差分模式总线。 总线被配置为不需要额外的线路，并且因此基本上相同的电路可以用于单端模式或差分模式。 此外，可选模式驱动器可以连接到不可选模式的接收器，反之亦然。 本发明可以被实现为可选择的驱动器，可选接收器或可选择的驱动器/接收器对。 本发明的装置和方法适用于单向和双向总线实现。 本发明使用相同的总线（即电线）和用于单端和差模操作模式的基本相同的电路。 当在单端模式下工作时，总线的数据宽度是在差分模式下工作时的数据宽度的两倍。
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公开(公告)号：US6134164A
公开(公告)日：2000-10-17
申请号：US296876
申请日：1999-04-22
CPC分类号： G11C7/065
摘要： The present invention addresses the foregoing need by providing a memory sensing circuit for accelerating a logic level transition of the complementary memory bit line of a complementary bit line pair having a full logic swing. The memory sensing circuit has a dual-rail circuit and at least one slew-rate acceleration circuit. The dual-rail circuit can be coupled across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines. The at least one slew-rate acceleration circuit is coupled to the dual-rail circuit. The conditioned signal is input to the slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive the conditioned signal. A feed-back loop transistor, having a gate terminal coupled to an output terminal of the inverter circuit is responsive to an output signal placed on the output terminal such that the slew-rate of the conditioned signal is accelerated.
摘要翻译： 本发明通过提供用于加速具有完整逻辑摆幅的互补位线对的互补存储器位线的逻辑电平转换的存储器感测电路来解决上述需要。 存储器感测电路具有双轨电路和至少一个压摆率加速电路。 双轨电路可以跨越互补位线对耦合，用于调节经历放置在任一位线上的逻辑状态转换的信号。 所述至少一个转换速率加速电路耦合到双轨电路。 调节信号被输入到转换速率加速电路，所述转换速率加速电路具有带有输入端的反相器电路，以接收调节信号。 具有耦合到反相器电路的输出端的栅极端的反馈回路晶体管响应放置在输出端子上的输出信号，使得调节信号的转换速率被加速。
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8.发明授权Method for skipping a latch in timing-sensitive dynamic circuits of a multi-clocked system with unspecific underlap requirement 失效在具有非特异性欠载要求的多时钟系统的时序敏感动态电路中跳过锁存器的方法公开(公告)号：US06737888B1
公开(公告)日：2004-05-18
申请号：US09435864
申请日：1999-11-08
IPC分类号： H03K1901
CPC分类号： H03K19/0963
摘要： A first clock stage in a circuit utilizes a second stage clock for triggering the falling edge of a first clock stage output. The output will not reset until both the first clock is low and the second clock are high due to the addition of the second clock signal. This is accomplished by adding a transistor and inverter to the first stage. The drain of a P-type FET is connected to source of the P-FET being controlled by the first clock through its gate. The additional P-FET is controlled by an inverted second clock signal. The clock signal is inverted by an inverter connected to the gate of the additional P-FET. Stability is provided to the first stage by creating a full keeper, which holds the output from the logic device in the first stage. A pair of transistors are connected by their drains to the output of the logic device. The transistors are controlled by an inverter, which is connected to the pairs' bases, wherein the inverter receives the output from the logic device. The transistor pair comprises one N-FET and P-FET.
摘要翻译： 电路中的第一时钟级利用第二级时钟来触发第一时钟级输出的下降沿。 由于添加了第二个时钟信号，第一个时钟为低电平而第二个时钟为高电平时，输出将不会复位。 这是通过在第一级添加晶体管和逆变器来实现的。 P型FET的漏极通过其栅极连接到由第一时钟控制的P-FET的源极。 附加的P-FET由反相的第二时钟信号控制。 时钟信号由连接到附加P-FET的栅极的反相器反相。 通过创建一个保持第一阶段的逻辑器件的输出的完整的保持器，将稳定性提供给第一阶段。 一对晶体管通过其漏极连接到逻辑器件的输出端。 晶体管由连接到对的基极的逆变器控制，其中逆变器接收来自逻辑器件的输出。 晶体管对包括一个N-FET和P-FET。
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公开(公告)号：US5831896A
公开(公告)日：1998-11-03
申请号：US767772
申请日：1996-12-17
IPC分类号： G11C11/412 , G11C11/00
CPC分类号： G11C11/412
摘要： A five transistor memory cell, is a single ended static random access memory (SRAM) cell. Reading and writing from the cell is implemented with one bit line along with word line read and word line write signals. One of the transistors within the memory cell is not coupled directly to ground, but is instead coupled to a controlled impedance node. This permits the affected transistor to float between ground and a high impedance state, which permits one bit line to write into the memory cell.
摘要翻译： 一个五晶体管存储单元，是单端静态随机存取存储器（SRAM）单元。 从单元读取和写入通过一条位线以及字线读取和字线写入信号来实现。 存储单元内的晶体管之一不直接耦合到地，而是耦合到受控阻抗节点。 这允许受影响的晶体管在地之间浮动和高阻抗状态，这允许一个位线写入存储单元。
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公开(公告)号：US06191620B1
公开(公告)日：2001-02-20
申请号：US09435064
申请日：1999-11-04
申请人： George McNeil Lattimore , Terry Lee Leasure , Younes John Lotfi , Robert Anthony Ross, Jr. , Gus Wai-Yan Yeung
发明人： George McNeil Lattimore , Terry Lee Leasure , Younes John Lotfi , Robert Anthony Ross, Jr. , Gus Wai-Yan Yeung
IPC分类号： G11C706
CPC分类号： H03K5/2481 , G11C7/062
摘要： A comparator circuit (40) includes a comparator network and a comparator enabling device (80) and may be integrated with a sense amplifier circuit (41). The comparator network is adapted to receive a complementary pair of reference data signals (B, B13) and a complementary pair of analog data signals (d1, d1b). An output of the comparator circuit (40) represents a comparison of the data represented by the reference data signals and the data represented by the analog data signals. The comparator output is generated in response to a comparator enable signal (SE) applied to the comparator enabling device (80) while the input data is applied to the comparator network. The comparator enable signal (SE) is applied at a time when the analog data signals (d1, d1b) have developed a minimum differential level.
摘要翻译： 比较器电路（40）包括比较器网络和比较器使能装置（80），并且可以与读出放大器电路（41）集成。 比较器网络适于接收互补的一对参考数据信号（B，B13）和互补的一对模拟数据信号（d1，d1b）。 比较器电路（40）的输出表示由参考数据信号表示的数据和由模拟数据信号表示的数据的比较。 响应于将比较器使能信号（SE）施加到比较器使能装置（80）而将输入数据施加到比较器网络而产生比较器输出。 当模拟数据信号（d1，d1b）产生最小差分电平时，施加比较器使能信号（SE）。
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