利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

25 条记录 (耗时 0.019 秒)

    Pulse detector which employs a self-resetting pulse amplifier
    21.
    发明授权
    Pulse detector which employs a self-resetting pulse amplifier 失效
    采用自复位脉冲放大器的脉冲检测器

    公开(公告)号：US07528357B2

    公开(公告)日：2009-05-05

    申请号：US11407376

    申请日：2006-04-19

    申请人： Behzad Razavi ,  Lawrence C. West ,  Bryan D. Ackland

    发明人： Behzad Razavi ,  Lawrence C. West ,  Bryan D. Ackland

    IPC分类号： H03G3/20

    CPC分类号： H01L27/144 ,  H03F3/08 ,  H03K5/1534 ,  H04B10/66

    摘要： A circuit including: an optical detector for detecting an optical pulse and generating therefrom a current pulse on an output; a pulse detector circuit having an input electrically connected to the optical detector and having an output for outputting a detection pulse in response to detecting the current pulse on its input, said pulse detector circuit including: a resettable amplifier including an input for receiving the current pulse from the optical detector, a reset terminal for resetting the amplifier after the amplifier detects the current pulse on its input, and an output for outputting a signal from which the detection pulse is derived; and a reset delay chain feeding back to the reset terminal of the resettable amplifier a feedback signal derived from the output signal of the resettable amplifier.

    摘要翻译： 一种电路，包括：光检测器，用于检测光脉冲并产生输出上的电流脉冲; 脉冲检测器电路，其具有电连接到所述光学检测器的输入端，并具有用于响应于检测其输入上的电流脉冲而输出检测脉冲的输出，所述脉冲检测器电路包括：可复位放大器，包括用于接收电流脉冲的输入 来自光检测器的复位端子，用于在放大器检测到其输入上的电流脉冲之后复位放大器，以及用于输出用于输出检测脉冲的信号的输出; 以及复位延迟链，其将可重置放大器的输出信号导出的反馈信号反馈到可复位放大器的复位端。

    Static random access memory sense amplifier
    22.
    发明授权
    Static random access memory sense amplifier 失效
    静态随机存取存储器读出放大器

    公开(公告)号：US5604705A

    公开(公告)日：1997-02-18

    申请号：US518055

    申请日：1995-08-22

    申请人： Bryan D. Ackland ,  Jay H. O'Neill

    发明人： Bryan D. Ackland ,  Jay H. O'Neill

    IPC分类号： G11C11/409 ,  G11C11/419 ,  G11C7/06

    CPC分类号： G11C11/419

    摘要： A memory sense amplifier for a static random access memory includes a pair of transistor amplifiers respective to the bit lines threading the memory. The power consumed is minimized without sacrificing speed of operation by temporarily connecting the source electrodes of the transistor amplifiers to the bit lines to allow them to track the states of the bit lines before a current path is completed to the drains of the transistors to allow them to draw current from the bit lines, thereby minimizing the time that the sense amplifiers are permitted to draw current from the bit lines. In addition, an economy of circuitry is achieved by eliminating the need for a separate latch circuit by disconnecting the sense amplifiers from the bit lines and thereafter enabling them to latch the information state read from the bit lines. The memory cycle is defined in four distinct phases ("PRECHARGE", "SENSE", "SELECT", and "HOLD"), instead of in two phases ("clock" and "select") followed by indeterminate length self-timed intervals as provided in prior art U.S. Pat. No. 5,309,395.

    摘要翻译： 用于静态随机存取存储器的存储读出放大器包括对应于穿过存储器的位线的一对晶体管放大器。 通过将晶体管放大器的源电极临时连接到位线，使消耗的功率最小化而不牺牲操作速度，以允许它们在电流路径完成之前跟踪晶体管的漏极以允许它们跟踪位线的状态，以允许它们 以从位线中抽出电流，从而最小化允许读出放大器从位线抽取电流的时间。 此外，通过将读出放大器与位线断开来消除对单独的锁存电路的需要，从而使它们能够锁存从位线读出的信息状态来实现电路的经济性。 存储周期在四个不同的阶段（“PRECHARGE”，“SENSE”，“SELECT”和“HOLD”）中定义，而不是两个阶段（“clock”和“select”），后面是不确定的长度自定时间 如现有技术的US Pat。 第5,309,395号。

    Random access memory system having high-speed serial data paths
    25.
    发明授权
    Random access memory system having high-speed serial data paths 失效
    具有高速串行数据路径的随机存取存储器系统

    公开(公告)号：US4412313A

    公开(公告)日：1983-10-25

    申请号：US226462

    申请日：1981-01-19

    申请人： Bryan D. Ackland ,  Neil H. E. Weste

    发明人： Bryan D. Ackland ,  Neil H. E. Weste

    IPC分类号： G11C11/34 ,  G11C7/10 ,  G11C8/04 ,  G11C11/401 ,  G11C11/417 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/1093 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/04 ,  G11C2207/107

    摘要： To substantially increase the bandwidth of a random access memory (RAM), a shift register is disposed within the memory array such that the shift register lies parallel to the word lines and is connected to at least individual ones of the bit lines contained within the array. Separate high-speed serial input and output lines are provided by the shift register. These lines are in addition to and operate independently of the slower speed input and output lines normally provided by the RAM. Through this arrangement, a row of data can be transferred to and from the memory array at a rate substantially faster than the single-bit access rate of the RAM.

    摘要翻译： 为了大大增加随机存取存储器（RAM）的带宽，移位寄存器被布置在存储器阵列内，使得移位寄存器平行于字线并且连接到阵列中包含的至少单个位线 。 单独的高速串行输入和输出线由移位寄存器提供。 这些线路通常由RAM通常提供的较慢速度的输入和输出线路进行补充和操作。 通过这种布置，可以以比RAM的单位访问速率快得多的速率将一行数据传送到存储器阵列和从存储器阵列传送。