公开(公告)号：US07558121B2

公开(公告)日：2009-07-07

申请号：US11694473

申请日：2007-03-30

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: G11C11/34

CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C16/22

Abstract: A flash memory device includes an array having memory cells arranged in rows and columns. A high voltage generator is configured to supply a high voltage to the array during a programming operation. Write buffers corresponding to selected memory cells drive the selected memory cells with a program voltage or a program-inhibition voltage in response to input data. Each write buffer consumes a dummy cell current when input data is program-inhibited data. A current-voltage conversion circuit connected to the write buffers through a common sensing line supplies a current to the write buffers as the dummy cell current through the common sensing line and outputs a voltage proportional to the current, supplied to the write buffers. A current sink circuit discharges a current from an output of the high voltage generator in response to a voltage output from the current-voltage conversion circuit.

Abstract translation: 闪速存储器件包括具有排列成行和列的存储单元的阵列。 高电压发生器被配置为在编程操作期间向阵列提供高电压。 对应于所选择的存储器单元的写缓冲器响应于输入数据以编程电压或编程禁止电压驱动所选存储单元。 当输入数据为程序禁止数据时，每个写入缓冲区消耗一个虚拟单元电流。 通过公共检测线连接到写入缓冲器的电流 - 电压转换电路通过公共检测线将电流作为虚拟单元电流提供给写入缓冲器，并输出与提供给写入缓冲器的电流成比例的电压。 电流吸收电路响应于来自电流 - 电压转换电路的电压输出，从高电压发生器的输出放电电流。

公开(公告)号：US07483303B2

公开(公告)日：2009-01-27

申请号：US11695132

申请日：2007-04-02

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C5/145

Abstract: A flash memory device including: a memory cell array having memory cells arranged in rows and columns; and a high voltage generator configured to generate a high voltage supplied into a source line of the memory cell array during a programming operation. The high voltage generator operates to vary the high voltage along an amount of current supplied into the memory cell array during the programming operation.

Abstract translation: 一种闪速存储器件，包括：具有以行和列排列的存储单元的存储单元阵列; 以及高压发生器，其被配置为在编程操作期间产生提供给所述存储单元阵列的源极线的高电压。 高电压发生器操作以在编程操作期间沿供给到存储单元阵列的电流量改变高电压。

公开(公告)号：US20080117689A1

公开(公告)日：2008-05-22

申请号：US11695132

申请日：2007-04-02

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C5/145

Abstract: A flash memory device including; a memory cell array having memory cells arranged in rows and columns; and a high voltage generator configured to generate a high voltage supplied into a source line of the memory cell array during a programming operation. The high voltage generator operates to vary the high voltage along an amount of current supplied into the memory cell array during the programming operation.

Abstract translation: 一种闪存装置，包括： 具有以行和列排列的存储单元的存储单元阵列; 以及高压发生器，其被配置为在编程操作期间产生提供给所述存储单元阵列的源极线的高电压。 高电压发生器操作以在编程操作期间沿供给到存储单元阵列的电流量改变高电压。

公开(公告)号：US20080117674A1

公开(公告)日：2008-05-22

申请号：US11694473

申请日：2007-03-30

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: G11C16/06

CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C16/22

Abstract: A flash memory device includes an array having memory cells arranged in rows and columns. A high voltage generator is configured to supply a high voltage to the array during a programming operation. Write buffers corresponding to selected memory cells drive the selected memory cells with a program voltage or a program-inhibition voltage in response to input data. Each write buffer consumes a dummy cell current when input data is program-inhibited data. A current-voltage conversion circuit connected to the write buffers through a common sensing line supplies a current to the write buffers as the dummy cell current through the common sensing line and outputs a voltage proportional to the current, supplied to the write buffers. A current sink circuit discharges a current from an output of the high voltage generator in response to a voltage output from the current-voltage conversion circuit.

Abstract translation: 闪速存储器件包括具有排列成行和列的存储单元的阵列。 高电压发生器被配置为在编程操作期间向阵列提供高电压。 对应于所选择的存储器单元的写缓冲器响应于输入数据以编程电压或编程禁止电压驱动所选存储单元。 当输入数据为程序禁止数据时，每个写入缓冲区消耗一个虚拟单元电流。 通过公共检测线连接到写入缓冲器的电流 - 电压转换电路通过公共检测线将电流作为虚拟单元电流提供给写入缓冲器，并输出与提供给写入缓冲器的电流成比例的电压。 电流吸收电路响应于来自电流 - 电压转换电路的电压输出，从高电压发生器的输出放电电流。

公开(公告)号：US07134358B2

公开(公告)日：2006-11-14

申请号：US10649809

申请日：2003-08-28

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: B62D1/18

CPC classification number: B62D1/184 ,  B62D1/187

Abstract: The present invention relates, in general, to a tilt steering apparatus for a vehicle, and more specifically, to a tilt steering apparatus for a vehicle, capable of adjusting the angle of a steering column by engaging a movable gear with a fixed gear or disengaging the movable gear from the fixed gear, using a lock slider that does a rectilinear motion by an operation lever. If the lock slider is separated from the operation lever, even when the operation lever rotates, the lock slider does a rectilinear motion only. Hence, the lock slider and the movable gear can always make the line contact with each other. Through this line contact, the supporting rigidity and the abrasion resistance of components can be improved.

Abstract translation: 本发明一般涉及用于车辆的倾斜转向装置，更具体地，涉及一种用于车辆的倾斜转向装置，其能够通过将可动齿轮与固定齿轮啮合或分离来调节转向柱的角度 来自固定齿轮的可动齿轮，使用通过操作杆进行直线运动的锁定滑块。 如果锁定滑块与操作杆分离，即使操作杆旋转，锁定滑块只能进行直线运动。 因此，锁定滑块和可动齿轮总能使线路彼此接触。 通过该线接触，可以提高部件的支撑刚性和耐磨性。

公开(公告)号：US20060049620A1

公开(公告)日：2006-03-09

申请号：US11003434

申请日：2004-12-06

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: B62D1/11 ,  B62D1/19

CPC classification number: B62D1/195

Abstract: A shock absorbing device for steering columns, which has a bracket and a capsule placed around a capsule locking slot of the bracket and fastened along with the bracket to a vehicle body by a locking bolt, is disclosed. The capsule includes an upper plate, a lower plate, and a connector which connects an end of the upper plate to an end of the lower plate. The shock absorbing device further includes a stopper which is provided between the upper plate and the lower plate of the capsule such that the stopper is placed in the capsule locking slot of the bracket. The upper plate of the capsule is bent at an outside edge thereof. The stopper is thinner than the bracket around the capsule locking slot. Furthermore, the upper plate and the lower plate of the capsule are configured such that the upper and lower plates are vertically aligned with each other at outside ends of extensions thereof.

Abstract translation: 公开了一种用于转向柱的减震装置，其具有支架和围绕支架的胶囊锁定槽并且通过锁定螺栓与支架一起固定到车体上的胶囊。 胶囊包括上板，下板和将上板的端部连接到下板的端部的连接器。 该减震装置还包括设置在胶囊的上板和下板之间的止动件，使得止动件被放置在支架的胶囊锁定槽中。 胶囊的上板在其外边缘处弯曲。 塞子比胶囊锁定槽周围的支架更薄。 此外，胶囊的上板和下板被构造成使得上板和下板在其延伸部的外端处彼此垂直对准。

公开(公告)号：US20060005005A1

公开(公告)日：2006-01-05

申请号：US11050477

申请日：2005-02-03

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: G06F9/00

CPC classification number: G06F9/4401 ,  G06F8/654 ,  G06F8/66

Abstract: A memory system and corresponding method for executing boot code stored therein are provided, the memory system including a mode decoder, a first memory in signal communication with the mode decoder, a second memory in signal communication with the mode decoder, and a mode generator in signal communication with the mode decoder for generating a signal indicative of selecting one of the first and second memories as the boot memory; and the method for executing boot code including initially booting the system from a first memory, programming a second memory for subsequent booting, programming a mode generator to subsequently boot the system from the second memory, and subsequently booting the system from the second memory.

公开(公告)号：US06975490B2

公开(公告)日：2005-12-13

申请号：US10429829

申请日：2003-05-06

Applicant: Byeong-Hoon Lee ,  Min-Ho So

Inventor： Byeong-Hoon Lee ,  Min-Ho So

IPC: G01R31/02 ,  F24F11/00 ,  F24F11/02 ,  G01R29/18 ,  H02H3/253 ,  H02H7/09 ,  H02H7/00

CPC classification number: H02H3/253 ,  F24F11/30 ,  H02H7/09

Abstract: In an apparatus and a method for detecting a phase state capable of improving reliability of an air conditioner by preventing an abnormal operation of the air conditioner by detecting a phase state (antiphase and open-phase) of three phase AC power supplied to the air conditioner and displaying the detected phase state, the apparatus includes a phase detector for detecting first, second and third phases of a three phase current; an interrupt detector for detecting a falling edge of a pulse signal corresponded to the third phase of the detected first, second and third phases, recognizing an interrupt occurrence by the third phase when the falling edge is detected and generating a counting signal; a counter for counting a pulse signal corresponded to the first and second phases on the basis of the interrupt occurred-third phase according to the counting signal; an antiphase/open-phase detector for detecting a state as a normal connection state, an antiphase state on the basis of a pulse signal corresponded to the first or second phase counted by the counter and detecting an open-phase state on the basis of the interrupt counting times; and a display unit for displaying a message indicating the antiphase state or the open-phase state or the normal connection state on a screen according to a control signal of the antiphase/open-phase detector.

Abstract translation: 在通过检测提供给空调器的三相AC电力的相位状态（反相和开相）来防止空调机的异常运行来检测能够提高空调的可靠性的相位状态的装置和方法中， 并显示所检测的相位状态，所述装置包括用于检测三相电流的第一，第二和第三相位的相位检测器; 用于检测对应于检测到的第一，第二和第三相位的第三相位的脉冲信号的下降沿的中断检测器，当检测到下降沿时识别出第三相位的中断发生并产生计数信号; 根据计数信号，根据中断发生的第三相位计数对应于第一和第二相的脉冲信号的计数器; 用于检测作为正常连接状态的状态的反相/开路相位检测器，基于对应于由计数器计数的第一或第二相位的脉冲信号的反相状态，并基于 中断计数次数; 以及显示单元，用于根据反相/开相检测器的控制信号在屏幕上显示指示反相状态或者开相状态或正常连接状态的信息。

公开(公告)号：US06831860B2

公开(公告)日：2004-12-14

申请号：US09997080

申请日：2001-11-28

Applicant: Byeong-Hoon Lee ,  Seung-Keun Lee

Inventor： Byeong-Hoon Lee ,  Seung-Keun Lee

IPC: G11C1604

CPC classification number: G11C16/0416 ,  G11C16/08

Abstract: A sector structure of a flash memory device minimizes a layout area in a chip without deteriorating a high-speed operation. The sector structure of the flash memory device includes a plurality of sectors, each sector including memory cell transistors in a cell array block sharing a common bulk region with transistors in a column decoder block.

Abstract translation: 闪存器件的扇区结构使芯片中的布局区域最小化，而不会降低高速操作。 闪存器件的扇区结构包括多个扇区，每个扇区包括与列解码器块中的晶体管共享公共体区的单元阵列块中的存储单元晶体管。

公开(公告)号：US5773852A

公开(公告)日：1998-06-30

申请号：US679564

申请日：1996-07-15

Applicant: Min-Koo Han ,  Byeong-Hoon Lee ,  Moo-Sup Lim ,  Yearn-Ik Choi ,  Jung-Eon Park ,  Won-Oh Lee

Inventor： Min-Koo Han ,  Byeong-Hoon Lee ,  Moo-Sup Lim ,  Yearn-Ik Choi ,  Jung-Eon Park ,  Won-Oh Lee

IPC: H01L29/78 ,  H01L29/72 ,  H01L29/739 ,  H01L29/786 ,  H01L29/74 ,  H01L31/111

CPC classification number: H01L29/7394

Abstract: A shorted anode lateral insulated gate bipolar transistor includes a semiconductor layer of a first conductivity type, a first current electrode, a second current electrode, a first insulation layer, a first gate electrode, a second gate electrode, a first high concentration impurity region of a second conductivity type, a low concentration impurity region of the second conductivity type, a first high concentration impurity region of the first conductivity type, a second high concentration impurity region of the second conductivity type, a third high concentration impurity region of the second conductivity type, and a second high concentration impurity region of the first conductivity type.

Abstract translation: 短路阳极横向绝缘栅双极晶体管包括第一导电类型的半导体层，第一电流电极，第二电流电极，第一绝缘层，第一栅极电极，第二栅极电极，第一高浓度杂质区域 第二导电类型的低浓度杂质区，第二导电类型的第一高浓度杂质区，第二导电类型的第一高浓度杂质区，第二导电类型的第二高浓度杂质区，第二导电类型的第二高浓度杂质区， 型和第一导电类型的第二高浓度杂质区。