公开(公告)号：US20080109700A1

公开(公告)日：2008-05-08

申请号：US11773214

申请日：2007-07-03

申请人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

发明人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

IPC分类号： G06F11/10

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C8/12

摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

摘要翻译： 半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。 存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。 模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。 奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。 数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为 检测并输出校正的读取数据。

公开(公告)号：US20080074918A1

公开(公告)日：2008-03-27

申请号：US11790011

申请日：2007-04-23

申请人： Yu-Hwan Ro ,  Kwang-Jin Lee ,  Sang-Beom Kang ,  Woo-Yeong Cho

发明人： Yu-Hwan Ro ,  Kwang-Jin Lee ,  Sang-Beom Kang ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C16/3486 ,  G11C2013/0076

摘要： In various methods of performing program operations in phase change memory devices, selected memory cells are repeatedly programmed to obtain resistance distributions having desired characteristics such as adequate sensing margins.

摘要翻译： 在相变存储器件中执行程序操作的各种方法中，选择的存储器单元被重复编程以获得具有所需特性（例如足够的感测裕度）的电阻分布。

公开(公告)号：US06898133B2

公开(公告)日：2005-05-24

申请号：US10179147

申请日：2002-06-26

申请人： Yong-Dae Park ,  Kwang-Jin Lee

发明人： Yong-Dae Park ,  Kwang-Jin Lee

IPC分类号： G11C5/00 ,  G11C29/00 ,  G11C29/48 ,  G11C7/00

CPC分类号： G11C29/006 ,  G11C5/00 ,  G11C29/48

摘要： A package map data outputting circuit of a semiconductor memory device embedded with a test circuit and a method for the same are provided. To improve the reliability of package map data and easily output a greater amount of the package map data, the package map data is stored to package map data registers at the wafer level and then output through the test circuit at the package level.

摘要翻译： 提供了嵌入有测试电路的半导体存储器件的封装映射数据输出电路及其方法。 为了提高封装图数据的可靠性，并且容易地输出更大量的封装映射数据，封装映射数据被存储到晶片级的封装映射数据寄存器，然后通过封装级的测试电路输出。

公开(公告)号：US08506722B2

公开(公告)日：2013-08-13

申请号：US13265148

申请日：2010-04-19

申请人： Kwang-Jin Lee

发明人： Kwang-Jin Lee

IPC分类号： B08B5/00

CPC分类号： B01D65/02 ,  B01D63/02 ,  B01D2315/06 ,  B01D2321/04 ,  B01D2321/162 ,  B01D2321/168 ,  B01D2321/185

摘要： A method for cleaning a filtering membrane, contaminated by contaminants including inorganic and organic materials during a fluid-filtering process, is disclosed, the method comprises cleaning the filtering membrane by using a first cleaning solution of pH 6˜9 so as to remove the organic material from the filtering membrane; and cleaning the filtering membrane by using a second acid cleaning solution so as to remove the inorganic material from the filtering membrane, wherein the cleaning method of the present invention uses the first cleaning solution having pH 6˜9 instead of a strong-alkaline cleaning solution so as to prevent the filtering membrane from being damaged, and also uses the cleaning solution maintained at a relatively low temperature instead of hot water so as to improve economical efficiency by reduction of energy consumption.

摘要翻译： 公开了一种在流体过滤过程中清洁被污染物包括无机和有机材料的过滤膜的方法，该方法包括使用pH6〜9的第一清洗液清洗过滤膜，以除去有机物 过滤膜材料; 并利用第二种酸性清洗液清洗过滤膜，以从过滤膜中除去无机材料，其中本发明的清洗方法使用pH6〜9的第一清洗液，而不是强碱性清洗液 以防止过滤膜被损坏，并且还使用维持在较低温度而不是热水的清洗溶液，从而通过降低能量消耗来提高经济效率。

公开(公告)号：US08218360B2

公开(公告)日：2012-07-10

申请号：US12582880

申请日：2009-10-21

申请人： Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

发明人： Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/004 ,  G11C7/1018 ,  G11C8/18 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004

摘要： Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.

摘要翻译： 提供了相变和电阻变化随机存取存储器件，其包括相变或电阻变化存储单元阵列和被配置为放大从相变存储单元阵列读取的数据的读出放大器。 这些随机存取存储器件被配置为从相变或电阻变化存储单元阵列的第一字线读取数据，并且在突发模式操作期间发生第一边界交叉时插入其中没有读取数据的虚拟脉冲串 。 还提供了以突发模式操作相变和/或电阻变化随机存取存储器件的相关方法。

公开(公告)号：US08190968B2

公开(公告)日：2012-05-29

申请号：US13099640

申请日：2011-05-03

申请人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

发明人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

IPC分类号： H03M13/00

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C8/12

摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

摘要翻译： 半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。 存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。 模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。 奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。 数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为 检测并输出校正的读取数据。

公开(公告)号：US08174878B2

公开(公告)日：2012-05-08

申请号：US13053471

申请日：2011-03-22

申请人： Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

发明人： Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2213/72

摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

摘要翻译： 提供了一种非易失性存储器及其相关编程方法。 非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。 写电路被配置为在第一程序操作期间使用内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二程序操作期间将第二逻辑状态数据写入第二组存储器单元 外部提供的升压电压。

公开(公告)号：US07949928B2

公开(公告)日：2011-05-24

申请号：US11773214

申请日：2007-07-03

申请人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

发明人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

IPC分类号： G11C29/00

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C8/12

摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

摘要翻译： 半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。 存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。 模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。 奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。 数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为 检测并输出校正的读取数据。

公开(公告)号：US20100124102A1

公开(公告)日：2010-05-20

申请号：US12582880

申请日：2009-10-21

申请人： Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

发明人： Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/004 ,  G11C7/1018 ,  G11C8/18 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004

摘要： Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.

摘要翻译： 提供了相变和电阻变化随机存取存储器件，其包括相变或电阻变化存储单元阵列和被配置为放大从相变存储单元阵列读取的数据的读出放大器。 这些随机存取存储器件被配置为从相变或电阻变化存储单元阵列的第一字线读取数据，并且在突发模式操作期间发生第一边界交叉时插入其中没有读取数据的虚拟脉冲串 。 还提供了以突发模式操作相变和/或电阻变化随机存取存储器件的相关方法。

公开(公告)号：US20090285008A1

公开(公告)日：2009-11-19

申请号：US12419934

申请日：2009-04-07

申请人： Hong-Sik Jeong ,  Kwang-Jin Lee ,  Dae-Won Ha ,  Gi-Tae Jeong ,  Jung-Hyuk Lee

发明人： Hong-Sik Jeong ,  Kwang-Jin Lee ,  Dae-Won Ha ,  Gi-Tae Jeong ,  Jung-Hyuk Lee

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C8/10 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3459 ,  G11C2013/0076

摘要： A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the received write data to the selected memory location occurs based on the monitored number of read cycles. Selectively pre-write verifying and writing of the received write data may include, for example, writing received write data to the selected memory cell region without pre-write verification responsive to the monitored number of read cycles being greater than a predetermined number of read cycles

摘要翻译： 监视应用于诸如可变电阻存储器件的存储器件的选定存储器位置的多个读周期。 接收要写入所选存储单元的写入数据。 基于所监视的读取周期数，对接收的写入数据进行选择性的预写入验证和写入。 选择性地预写入验证和写入所接收的写入数据可以包括例如将接收到的写入数据写入所选择的存储器单元区域，而无需预写入验证，响应于所监视的读取周期数大于预定数量的读取周期