公开(公告)号：US07248079B2

公开(公告)日：2007-07-24

申请号：US11285800

申请日：2005-11-23

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03K19/0175

CPC分类号： H04L25/0276

摘要： A differential buffer circuit includes a current source, a current sink, and a switching circuit connected to the current source at a first node and connected to the current sink at a second node. The switching circuit is operative to selectively control a direction of current flowing through differential outputs of the buffer circuit in response to at least a first control signal. The buffer circuit further includes a common mode detection circuit and a common mode control circuit. The common mode detection circuit is operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage. The common mode control circuit includes a first terminal connected to the current source and a second terminal connected to the current sink. The common mode control circuit is operative to selectively control the output common mode voltage of the buffer circuit as a function of the second control signal.

公开(公告)号：US6087853A

公开(公告)日：2000-07-11

申请号：US100939

申请日：1998-06-22

申请人： Carol A. Huber ,  Bernard L. Morris ,  Bijit T. Patel

发明人： Carol A. Huber ,  Bernard L. Morris ,  Bijit T. Patel

IPC分类号： H03K19/00 ,  H03K19/0175

CPC分类号： H03K19/0005

摘要： CMOS technology is used to create a controlled output impedance output buffer circuit. An output buffer driver uses buffer circuits having impedance elements with linear characteristics. A control circuit uses a known impedance load to control the impedance of the buffer circuits. The control circuit monitors a known current flowing through the known impedance load to determine whether the output buffer circuit's output impedance needs to be adjusted to match a transmission line's impedance. Adjustments occur when the control circuit generates control signals to turn on or off various buffer circuits (and their impedance elements) contained within the output driver. In doing so, the output buffer circuit ensures that its output impedance will match the impedance of a transmission line over the entire range of output voltages regardless of the variations caused by the manufacturing process, operation temperature and power supply voltage.

摘要翻译： CMOS技术用于创建受控输出阻抗输出缓冲电路。 输出缓冲器驱动器使用具有线性特性的阻抗元件的缓冲电路。 控制电路使用已知的阻抗负载来控制缓冲电路的阻抗。 控制电路监测流过已知阻抗负载的已知电流，以确定输出缓冲电路的输出阻抗是否需要调整以匹配传输线的阻抗。 当控制电路产生控制信号以导通或关闭包含在输出驱动器内的各种缓冲电路（及其阻抗元件）时，发生调整。 在这样做时，输出缓冲电路确保其输出阻抗将与输出电压的整个范围内的传输线的阻抗匹配，而不管制造过程，操作温度和电源电压引起的变化如何。

公开(公告)号：US5381062A

公开(公告)日：1995-01-10

申请号：US144594

申请日：1993-10-28

申请人： Bernard L. Morris

发明人： Bernard L. Morris

IPC分类号： H03K19/003 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/0948 ,  H03K19/0185

CPC分类号： H03K19/00315 ,  H03K19/09429 ,  H03K19/0948

摘要： An integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to a second node, and a second field effect transistor for protecting the first transistor from voltages applied to the first node and greater than a predetermined nominal voltage. The second transistor includes a drain connected to the second node, a source connected to the first node, and a gate connected to a third node. A constant voltage source is coupled to the third node and supplies a gate voltage to the gate of the second transistor such that a drain-source path of the second transistor does not conduct while voltage applied to the first node is generally less than the gate voltage plus a threshold voltage of the second transistor. The constant voltage source comprises a third field effect transistor having a drain and a gate connected to the third node, and a source coupled to a first power supply voltage, such that the gate voltage is substantially equal to the first power supply voltage minus a threshold voltage of the third transistor.

摘要翻译： 公开了一种集成电路，其包括具有连接到第一节点的源极和连接到第二节点的栅极的第一场效应晶体管，以及用于保护第一晶体管免受施加到第一节点的电压的第二场效应晶体管， 预定额定电压。 第二晶体管包括连接到第二节点的漏极，连接到第一节点的源极和连接到第三节点的栅极。 恒定电压源耦合到第三节点并且将栅极电压提供给第二晶体管的栅极，使得第二晶体管的漏极 - 源极路径不导通，而施加到第一节点的电压通常小于栅极电压 加上第二晶体管的阈值电压。 恒压源包括第三场效应晶体管，其具有连接到第三节点的漏极和栅极，以及耦合到第一电源电压的源极，使得栅极电压基本上等于第一电源电压减去阈值 第三晶体管的电压。

公开(公告)号：US07590961B2

公开(公告)日：2009-09-15

申请号：US11774022

申请日：2007-07-06

申请人： Martin J. Gasper, Jr. ,  Bernard L. Morris

发明人： Martin J. Gasper, Jr. ,  Bernard L. Morris

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  H03K5/1565 ,  H03K19/00323

摘要： An integrated circuit comprises digital circuitry having at least one digital logic cell and at least one skew adjusting cell. The skew adjusting cell is configured to adjust the skew of a signal in the digital circuitry of the integrated circuit to a desired amount. The digital logic cell and the skew adjusting cell are selected from a cell library.

摘要翻译： 集成电路包括具有至少一个数字逻辑单元和至少一个偏斜调整单元的数字电路。 偏斜调整单元被配置为将集成电路的数字电路中的信号的偏斜调整到期望的量。 从单元库中选择数字逻辑单元和偏斜调整单元。

公开(公告)号：US07551020B2

公开(公告)日：2009-06-23

申请号：US11755955

申请日：2007-05-31

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Antonio M. Marques ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Antonio M. Marques ,  Bernard L. Morris

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H03K19/00384 ,  H04L5/16 ,  H04L25/0264

摘要： A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.

摘要翻译： 用于补偿至少第一MOS器件的输出阻抗的补偿电路，其中PVT变化对其可能经受的PVT变化包括：第一电流源，其产生具有基本恒定值的第一电流和产生第一MOS器件的第二电流源 第二电流具有可被编程为呈现给第二电流源的至少一个控制信号的函数的值。 比较器连接到第一和第二电流源的相应输出，并且可操作以测量第一和第二电流的相应值之间的差，并产生指示第一电流和第二电流的相对幅度的输出信号。 连接在比较器和第二电流源之间的反馈装置中的处理器接收比较器产生的输出信号，并产生用于根据输出信号控制第二电流的控制信号。 处理器可操作以控制第二电流的值，使得第二电流基本上等于第一电流。

公开(公告)号：US07397279B2

公开(公告)日：2008-07-08

申请号：US11342175

申请日：2006-01-27

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Joseph E. Simko

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Joseph E. Simko

IPC分类号： H03K19/0175 ,  H03K5/00

CPC分类号： H03K19/017509 ,  H03K3/356104

摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp circuit is connected between the input stage and the latch circuit. The voltage clamp circuit is operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies.

摘要翻译： 用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，该输入级包括至少一个具有第一阈值电压 相关联。 电压电平转换器电路还包括锁存电路，其操作以存储表示输入信号的逻辑状态的信号，所述锁存电路包括具有与其相关联的第二阈值电压的至少一个晶体管器件，所述第二阈值电压大于 第一阈值电压。 电压钳位电路连接在输入级和锁存电路之间。 电压钳位电路用于限制输入级两端的电压，输入级两端的电压幅度作为第一和第二电压源之间的电压差的函数被控制。

公开(公告)号：US07068074B2

公开(公告)日：2006-06-27

申请号：US10881192

申请日：2004-06-30

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Antonio M. Marques ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Antonio M. Marques ,  Bernard L. Morris

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K3/356113 ,  H03K17/102

摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level includes an input stage for receiving the input signal. The input stage includes at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logical state of the input signal. The latch circuit includes at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp is operatively connected between the input stage and the latch circuit, the voltage clamp being configured to limit a voltage across the input stage based, at least in part, on a control signal presented thereto. The voltage level translator circuit includes a reference generator circuit for generating the control signal, a steady state value of the control signal being substantially equal to the first voltage level. The reference generator circuit is configured to adjust a voltage level of the control signal in response to the input signal.

摘要翻译： 用于将参考第一电压电平的输入信号转换为参考第二电压电平的输出信号的电压电平转换器电路包括用于接收输入信号的输入级。 输入级包括具有与其相关联的第一阈值电压的至少一个晶体管器件。 电压电平转换器电路还包括可操作地存储表示输入信号的逻辑状态的信号的锁存电路。 锁存电路包括具有与其相关联的第二阈值电压的至少一个晶体管器件，第二阈值电压大于第一阈值电压。 电压钳被可操作地连接在输入级和锁存电路之间，电压钳被配置成至少部分地基于呈现给输入级的控制信号来限制跨输入级的电压。 电压电平转换器电路包括用于产生控制信号的参考发生器电路，控制信号的稳态值基本上等于第一电压电平。 参考发生器电路被配置为响应于输入信号调整控制信号的电压电平。

公开(公告)号：US5933027A

公开(公告)日：1999-08-03

申请号：US879212

申请日：1997-06-19

申请人： Bernard L. Morris ,  Bijit T. Patel

发明人： Bernard L. Morris ,  Bijit T. Patel

IPC分类号： H01L27/04 ,  H01L21/822 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/00315

摘要： An integrated circuit is implemented in a low-voltage technology and has an output driver. The output driver has circuitry adapted to generate an output voltage at an output node (e.g., PAD in FIG. 1) based on an input voltage (e.g., A). Within the output driver, a transistor is configured to limit the drain-to-source voltage drop across another transistor to enable the integrated circuit to tolerate, at its output node, voltages of magnitude up to two times the operating voltage of the integrated circuit. The invention enables low-voltage integrated circuits to be interfaced with other circuitry implemented in a relatively high-voltage technology, without suffering the adverse effects that can otherwise result in the low-voltage circuitry from such interfacing.

摘要翻译： 集成电路采用低压技术实现，并具有输出驱动器。 输出驱动器具有适于基于输入电压（例如，A）在输出节点（例如，图1中的PAD）产生输出电压的电路。 在输出驱动器内，晶体管被配置为限制跨另一晶体管的漏极 - 源极电压降，以使得集成电路在其输出节点容忍高达集成电路的工作电压的两倍的电压。 本发明使得低电压集成电路能够与在相对高压技术中实现的其它电路接口，而不会产生不利影响，否则可能导致低压电路不受这种接口的影响。

公开(公告)号：US5894234A

公开(公告)日：1999-04-13

申请号：US846390

申请日：1997-04-30

申请人： Bernard L. Morris

发明人： Bernard L. Morris

IPC分类号： H03K3/3565 ,  H03K5/24 ,  H03F3/45 ,  H03F3/16

CPC分类号： H03K5/2481 ,  H03K3/3565

摘要： A differential comparator having a low-offset comparator and two processing paths, each of which receives one of the two primary inputs to the differential comparator and generates one of the two inputs to the low-offset comparator. The output of the low-offset comparator is the output of the differential comparator. Each processing path is capable of (1) generating an offset voltage and (2) turning on and off the generation of that offset voltage. In a preferred embodiment, each processing path has a passive resistor that generates the offset voltage and a pair of shunt transistors that selectively shorts out the passive resistor. The output of the low-offset comparator is connected (either directly or indirectly through an inverter) to the gates of the shunt transistors. The shunt transistors are therefore controlled by the output of the low-offset comparator. In each of two modes of operation, a different one of the passive resistors is "on" while the other passive resistor is "off." The result is a differential comparator that operates with hysteresis. The currents passing through the passive resistors to generate the offset voltages are mirrored from a current source that is controlled by a reference voltage. As such, the offset voltages can be controlled by adjusting the reference voltage. The differential comparator is capable therefore of operating with fixed and controllable hysteresis.

摘要翻译： 具有低偏移比较器和两个处理路径的差分比较器，每个处理路径接收到差分比较器的两个主要输入中的一个，并产生两个输入中的一个到低偏移比较器。 低偏移比较器的输出是差分比较器的输出。 每个处理路径能够（1）产生偏移电压和（2）打开和关闭该偏移电压的产生。 在优选实施例中，每个处理路径具有产生偏移电压的无源电阻器和选择性地使无源电阻器短路的一对分流晶体管。 低偏移比较器的输出端（直接或间接通过反相器）连接到分流晶体管的栅极。 因此，分流晶体管由低偏移比较器的输出控制。 在两种工作模式中，不同的一种无源电阻为“开”，而另一种无源电阻为“关闭”。 结果是一个差分比较器以滞后运行。 通过无源电阻产生偏移电压的电流与由参考电压控制的电流源相反。 因此，可以通过调整参考电压来控制偏移电压。 差分比较器因此能够以固定和可控的滞后运行。

公开(公告)号：US5334885A

公开(公告)日：1994-08-02

申请号：US3751

申请日：1993-01-13

申请人： Bernard L. Morris

发明人： Bernard L. Morris

IPC分类号： H03M1/36 ,  H03K19/003 ,  H03K17/16 ,  H03K19/092

CPC分类号： H03K19/00384

摘要： The number of active switching elements in a buffer is automatically varied to compensate for variations in the manufacturing process, operating temperature, and power supply voltage. For this purpose, a reference voltage which is proportional to the speed of a switching transistor is applied to an analog-to-digital (A/D) converter. The A/D converter may be implemented with a simple resistor divider and comparators, all of which can be made on-chip. The resistor dividers are chosen such that at worst-case slow conditions all the comparators have high outputs. As the process/temperature/voltage changes, the reference voltage also increases. This successively turns off sections of the switching transistor, thereby slowing down the response of the buffer. Since the control leads are digital, they are not susceptible to noise as they are routed around a chip full of noisy signals. The digital control signals may be latched, and the control circuitry powered down to zero for powersensitive applications.

摘要翻译： 缓冲器中的有源开关元件的数量自动变化以补偿制造工艺，工作温度和电源电压的变化。 为此，将与开关晶体管的速度成比例的参考电压施加到模数（A / D）转换器。 A / D转换器可以用简单的电阻分压器和比较器来实现，所有这些都可以在片上制造。 选择电阻分压器，使得在最差情况下，所有比较器都具有较高的输出。 随着过程/温度/电压的变化，参考电压也会增加。 这继续关闭开关晶体管的部分，从而减慢缓冲器的响应。 由于控制引线是数字的，它们不会受到噪声的影响，因为它们绕着充满噪声信号的芯片布线。 数字控制信号可能被锁存，并且控制电路对于功率敏感应用而降低到零。