公开(公告)号：US5418175A

公开(公告)日：1995-05-23

申请号：US239366

申请日：1994-05-06

申请人： Chen-Chiu Hsue ,  Gary Hong

发明人： Chen-Chiu Hsue ,  Gary Hong

IPC分类号： H01L21/8246 ,  H01L27/112

CPC分类号： H01L27/112

摘要： A semiconductor device manufactured by the process including a semiconductor substrate, which comprises the steps of forming buried bit lines below the surface of said semiconductor substrate forming an individual source and drain regions; forming a gate oxide layer on the surface of the substrate; forming a first conductive structure on the gate oxide layer; forming an insulating structure in contact with the first conductive structure; removing material from the surface of the first conductive structure to expose at least a portion of the surface beneath the first conductive structure; and forming on the remaining structure on the semiconductor substrate metal line structures having edges vertically aligned with and above the source and drain regions in the buried bit lines; whereby a compound conductive structure is provided on the semiconductor substrate.

摘要翻译： 一种由包括半导体衬底的工艺制造的半导体器件，包括以下步骤：在形成单个源极和漏极区域的所述半导体衬底的表面下方形成掩埋位线; 在所述基板的表面上形成栅氧化层; 在所述栅极氧化物层上形成第一导电结构; 形成与所述第一导电结构接触的绝缘结构; 从第一导电结构的表面去除材料以暴露第一导电结构下面的表面的至少一部分; 并且在所述半导体衬底金属线结构上的剩余结构上形成具有与所述掩埋位线中的所述源极和漏极区域垂直对准的边缘的边缘; 由此在半导体衬底上提供复合导电结构。

公开(公告)号：US5393233A

公开(公告)日：1995-02-28

申请号：US92190

申请日：1993-07-14

申请人： Gary Hong ,  Ming-Tzong Yang ,  Chen-Chiu Hsue

发明人： Gary Hong ,  Ming-Tzong Yang ,  Chen-Chiu Hsue

IPC分类号： H01L21/8246 ,  H01L21/70

CPC分类号： H01L27/1126

摘要： In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.

摘要翻译： 根据本发明，双重多晶法用于将相同硅区上的掩埋位线ROM的存储密度加倍。 特别地，减小字线间距以在垂直于字线的方向上增加单元密度。 本发明采用自对准方法进行ROM码植入和通过化学机械抛光（CMP）进行多平面化，以实现自对准双多重字线结构。

公开(公告)号：US5667940A

公开(公告)日：1997-09-16

申请号：US746147

申请日：1996-11-06

申请人： Chen-Chiu Hsue ,  Gary Hong

发明人： Chen-Chiu Hsue ,  Gary Hong

IPC分类号： G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/3213 ,  G03F7/26

CPC分类号： H01L21/32139 ,  G03F7/0035 ,  H01L21/0271 ,  H01L21/0274 ,  G03F7/40

摘要： A new photolithographic process using the method of photoresist double coating to fabricate fine lines with narrow spacing is described. A layer to be etched is provided overlying a semiconductor substrate. The layer to be etched is coated with a first layer of photoresist and baked. The first photoresist layer is exposed to actinic light through openings in a mask and developed to produce the desired first pattern on the surface of the first photoresist wherein the openings have a minimum width of the resolution limit plus two times the misalignment tolerance of the photolithography process. The layer to be etched is coated with a second photoresist layer where the layer to be etched is exposed within the openings in the first photoresist layer. The second photoresist layer is exposed to actinic light through openings in a mask and developed to produce the desired second pattern on the surface of the second photoresist wherein the second pattern alternates with the first photoresist pattern and wherein the spacing between the first and second patterned photoresist coatings has a width equal to the misalignment tolerance. The misalignment tolerance is much smaller than the resolution limit so the line spacing achieved is narrower than the resolution limit of the photolithography process.

摘要翻译： 描述了使用光致抗蚀剂双涂层的方法制造窄间距的细线的新的光刻工艺。 将要蚀刻的层设置在半导体衬底上。 待蚀刻的层被涂覆有第一层光致抗蚀剂并烘烤。 第一光致抗蚀剂层通过掩模中的开口暴露于光化光，并显影以在第一光致抗蚀剂的表面上产生所需的第一图案，其中开口具有分辨率极限的最小宽度加上光刻工艺的不对准公差的两倍 。 待蚀刻的层被涂覆有第二光致抗蚀剂层，其中待蚀刻的层暴露在第一光致抗蚀剂层的开口内。 第二光致抗蚀剂层通过掩模中的开口暴露于光化光，并显影以在第二光致抗蚀剂的表面上产生所需的第二图案，其中第二图案与第一光致抗蚀剂图案交替，并且其中第一和第二图案化光致抗蚀剂之间的间隔 涂层的宽度等于不对准公差。 不对准公差远小于分辨率极限，所以实现的线间距窄于光刻工艺的分辨率极限。

公开(公告)号：US5631481A

公开(公告)日：1997-05-20

申请号：US435194

申请日：1995-05-05

申请人： Chen-Chiu Hsue ,  Gary Hong

发明人： Chen-Chiu Hsue ,  Gary Hong

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L29/788

CPC分类号： H01L27/112

摘要： A semiconductor device manufactured by the process including a semiconductor substrate, which comprises the steps of forming buried bit lines below the surface of said semiconductor substrate forming individual source and drain regions; forming a gate oxide layer on the surface of the substrate; forming a first conductive structure on the gate oxide layer; forming an insulating structure in contact with the first conductive structure; removing material from the surface of the first conductive structure to expose at least a portion of the surface beneath the first conductive structure; and forming on the remaining structure on the semiconductor substrate metal line structures having edges vertically aligned with and above the source and drain regions in the buried bit lines; whereby a compound conductive structure is provided on the semiconductor substrate.

摘要翻译： 一种由包括半导体衬底的工艺制造的半导体器件，包括以下步骤：在形成各个源极和漏极区域的所述半导体衬底的表面下面形成掩埋位线; 在所述基板的表面上形成栅氧化层; 在所述栅极氧化物层上形成第一导电结构; 形成与所述第一导电结构接触的绝缘结构; 从第一导电结构的表面去除材料以暴露第一导电结构下面的表面的至少一部分; 并且在所述半导体衬底金属线结构上的剩余结构上形成具有与所述掩埋位线中的所述源极和漏极区域垂直对准的边缘的边缘; 由此在半导体衬底上提供复合导电结构。

公开(公告)号：US5460999A

公开(公告)日：1995-10-24

申请号：US254535

申请日：1994-06-06

申请人： Gary Hong ,  Chen-Chiu Hsue

发明人： Gary Hong ,  Chen-Chiu Hsue

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for fabricating a capacitor having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multi-layer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a fin-like bottom capacitor electrode. A high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses having the bottom electrode forming therein fin-shaped top capacitor electrode and completing a dynamic random access memory (DRAM) cell. This method also eliminates the need to plasma etch to the source/drain contact during the fabrication of the capacitor, thereby improving reliability and making a more manufacturable process.

摘要翻译： 实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造具有鳍状电极的电容器的方法。 电容器制造在具有有源器件区域的硅衬底上。 器件区域包含一个金属氧化物半导体场效应晶体管（MOSFET），其中一个电容器对准器件区域中与MOSFET的源极/漏极对准并接触。 通过在存储电容器区域和凹陷交替层上形成多层绝缘体结构，然后使用该形式作为形成鳍状底部电容器电极的模具，电容器增加电容。 作为电极间电介质，在底部电极上沉​​积高介电常数绝缘体。 顶部电容器电极通过沉积掺杂多晶硅层而形成，掺杂多晶硅层还填充具有底部电极的凹陷，其中形成有鳍状顶部电容器电极并完成动态随机存取存储器（DRAM）单元。 该方法也消除了在制造电容器期间对源极/漏极接触进行等离子体蚀刻的需要，从而提高可靠性并制造更可制造的工艺。

公开(公告)号：US5436185A

公开(公告)日：1995-07-25

申请号：US289647

申请日：1994-08-12

申请人： Chen-Chiu Hsue ,  Gary Hong

发明人： Chen-Chiu Hsue ,  Gary Hong

IPC分类号： H01L27/112 ,  H01L21/265

CPC分类号： H01L27/112

摘要： A semiconductor ROM device on a semiconductor substrate includes an array of parallel bit lines oriented in a first direction. A blanket word line layer formed on the device is covered with a word line mask with word line patterns orthogonal to the bit lines used during etching of word line layer to form word lines. A blanket glass layer is formed over the device and then covered with a patterned negative negative code implant mask. A silicon dioxide layer is formed on the blanket glass layer around the patterned negative negative code implant mask. The negative negative code implant mask is removed leaving a ROM code opening through the silicon dioxide layer, whereby the silicon dioxide layer forms a ROM code implant mask. The ROM code opening is centered on a word line conductor, and a code ion implant of dopant is made through the ROM code opening forming a code implant doped region in the substrate below the word line. The silicon dioxide layer is formed by liquid phase deposition.

摘要翻译： 半导体衬底上的半导体ROM器件包括沿第一方向定向的并行位线的阵列。 形成在器件上的粗糙字线层被字线掩模覆盖，字线模式与字线层蚀刻期间使用的位线正交的字线图案形成字线。 在该器件上形成覆盖玻璃层，然后用图案化负的代码植入掩模覆盖。 在图案化负的代码注入掩模周围的覆盖玻璃层上形成二氧化硅层。 去除负的负码植入掩模，留下通过二氧化硅层开放的ROM码，由此二氧化硅层形成ROM码植入掩模。 ROM代码开口以字线导体为中心，并通过形成在字线下方的衬底中的代码注入掺杂区域的ROM代码开口进行掺杂剂的代码离子注入。 二氧化硅层通过液相沉积形成。

公开(公告)号：US5364808A

公开(公告)日：1994-11-15

申请号：US192364

申请日：1994-02-07

申请人： Ming-Tzong Yang ,  Chen-Chiu Hsue ,  Gary Hong

发明人： Ming-Tzong Yang ,  Chen-Chiu Hsue ,  Gary Hong

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/266

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： Ions of dopant are implanted into predetermined locations in a doped semiconductor substrate in sufficient concentration to form a buried conductor regions. A thick dielectric layer overlies the surface of the doped substrate. A first polysilicon layer is formed and patterned on the silicon dioxide layer by a mask and etching to form conductor lines, covered by a dielectric. A second polysilicon layer is formed on the second dielectric layer and patterned to form a first capacitor plate. A third dielectric layer is formed on the surface of the second polysilicon layer. A third polysilicon layer is formed on the third dielectric layer and patterned to form a top capacitor plate. A layer of BPSG is deposited upon the third layer of polysilicon.

摘要翻译： 掺杂剂的离子以足够的浓度注入掺杂半导体衬底中的预定位置以形成掩埋导体区域。 厚电介质层覆盖在掺杂衬底的表面上。 通过掩模和蚀刻在二氧化硅层上形成并图案化第一多晶硅层以形成由电介质覆盖的导体线。 在第二电介质层上形成第二多晶硅层并构图以形成第一电容器板。 在第二多晶硅层的表面上形成第三电介质层。 在第三电介质层上形成第三多晶硅层并构图以形成顶部电容器板。 BPSG层沉积在第三层多晶硅上。

公开(公告)号：US06720267B1

公开(公告)日：2004-04-13

申请号：US10249149

申请日：2003-03-19

申请人： Anchor Chen ,  Gary Hong

发明人： Anchor Chen ,  Gary Hong

IPC分类号： H01L21311

CPC分类号： B81C1/0015 ,  B81B2201/047

摘要： A cantilever beam type micro-electromechanical system (MEMS) is formed on a substrate. Two first electrodes are formed in a first dielectric layer on the substrate and a waveguide line is formed between the first electrodes. A patterned sacrificial layer and an arm layer are formed on the substrate. Two second electrodes and a second dielectric layer are formed in the arm layer, and an optical grating is formed in the second dielectric layer. Finally, a cap layer is formed on the substrate, and the patterned sacrificial layer is removed.

摘要翻译： 在基板上形成悬臂梁型微机电系统（MEMS）。 两个第一电极形成在衬底上的第一电介质层中，并且在第一电极之间形成波导线。 在基板上形成图案化的牺牲层和臂层。 在臂层中形成两个第二电极和第二电介质层，并且在第二电介质层中形成光栅。 最后，在衬底上形成覆盖层，去除图案化的牺牲层。

公开(公告)号：US06235576B1

公开(公告)日：2001-05-22

申请号：US09241522

申请日：1999-02-01

申请人： Gary Hong ,  Anchor Chen

发明人： Gary Hong ,  Anchor Chen

IPC分类号： H01L2120

CPC分类号： H01L28/92 ,  H01L21/76895 ,  H01L27/10852

摘要： A method for manufacturing a cylindrical capacitor on a substrate includes the steps of providing a semiconductor substrate having a first conductive layer thereon, and then forming an insulation layer over the first conductive layer. The insulation layer can be a silicon nitride layer. The insulation layer is patterned to leave a portion of the patterned insulation layer above the node contact region. Thereafter, spacers are formed on the sidewalls of the patterned insulation layer such that the spacers are formed from a material that differs from the insulation layer and the first conductive layer. Next, an etching operation is conducted using the patterned insulation layer and the spacers as a mask to remove a portion of the first conductive layer. After that, the patterned insulation layer is removed. Then, a second etching operation is carried out using the spacers as a mask so that some more material from the upper portion of the first conductive layer is removed. Ultimately, a cylindrical shape structure that serves as the lower electrode of a capacitor is formed. Finally, the spacers are removed, and then a dielectric layer and a second conductive layer are sequentially formed over the cylindrical lower electrode to complete the fabrication of a cylindrical capacitor.

摘要翻译： 一种用于在基板上制造圆柱形电容器的方法包括以下步骤：在其上提供具有第一导电层的半导体衬底，然后在第一导电层上形成绝缘层。 绝缘层可以是氮化硅层。 将绝缘层图案化以将图案化绝缘层的一部分留在节点接触区域上方。 此后，在图案化绝缘层的侧壁上形成间隔物，使得间隔物由与绝缘层和第一导电层不同的材料形成。 接下来，使用图案化绝缘层和间隔物作为掩模进行蚀刻操作以去除第一导电层的一部分。 之后，去除图案化绝缘层。 然后，使用间隔物作为掩模进行第二蚀刻操作，从而去除来自第一导电层的上部的一些更多的材料。 最终，形成用作电容器的下电极的圆柱形结构。 最后，去除间隔物，然后在圆柱形下电极上依次形成电介质层和第二导电层，以完成圆柱形电容器的制造。

公开(公告)号：US6037234A

公开(公告)日：2000-03-14

申请号：US23879

申请日：1998-02-13

申请人： Gary Hong ,  Anchor Chen

发明人： Gary Hong ,  Anchor Chen

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/20 ,  H01L21/28 ,  H01L21/44

CPC分类号： H01L27/10852 ,  H01L28/91 ,  H01L21/76807

摘要： A method of fabricating a capacitor in a DRAM. A semiconductor substrate having a metal-oxide-semiconductor is provided. Using only one photolithography process, a bottom electrode is formed. By forming a dielectric layer over the substrate, and a poly-silicon layer on the dielectric layer, a capacitor is formed.

摘要翻译： 一种在DRAM中制造电容器的方法。 提供具有金属氧化物半导体的半导体衬底。 仅使用一个光刻工艺，形成底部电极。 通过在基板上形成电介质层，在电介质层上形成多晶硅层，形成电容器。