-
21.发明申请MECHANISM FOR FACILITATING DYNAMIC MULTI-MODE MEMORY PACKAGES IN MEMORY SYSTEMS 有权在存储系统中促进动态多模式存储器包的机制公开(公告)号：US20140006770A1
公开(公告)日：2014-01-02
申请号：US13539179
申请日：2012-06-29
IPC分类号： G06F9/06
CPC分类号： G06F12/063 , G06F12/0607
摘要： A mechanism is described for facilitating dynamic multi-mode memory packages in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes maintaining a plurality of memory modes on a single memory package at a motherboard of a computing system. The plurality of memory modes is associated with a plurality of physical organizations of memory devices. The method may further include receiving a request to switch from a first memory mode to a second memory mode of the plurality of memory mode, and dynamically switching from the first memory mode to the second memory mode, in response to the request.
摘要翻译： 描述了根据本发明的一个实施例的用于促进存储器系统中的动态多模式存储器包的机制。 本发明的实施例的方法包括在计算系统的主板上的单个存储器包上维护多个存储器模式。 多个存储器模式与存储器设备的多个物理组织相关联。 该方法还可以包括接收从多个存储器模式的第一存储器模式切换到第二存储器模式的请求，以及响应于该请求动态地从第一存储器模式切换到第二存储器模式。
-
公开(公告)号：US20140006729A1
公开(公告)日：2014-01-02
申请号：US13997399
申请日：2012-04-30
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0683 , G06F13/161 , G06F13/1684 , G06F13/1694 , G06F13/382 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, a system on a chip (SoC) includes a plurality of processor cores and a memory controller to control communication between the SoC and a memory coupled to the memory controller. The memory controller may be configured to send mirrored command and address signals to a first type of memory device and to send non-mirrored control and address signals to a second type of memory device. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，芯片上的系统（SoC）包括多个处理器核心和存储器控制器，用于控制SoC与耦合到存储器控制器的存储器之间的通信。 存储器控制器可以被配置为向第一类型的存储器件发送镜像命令和地址信号，并将非镜像控制和地址信号发送到第二类型的存储器件。 描述和要求保护其他实施例。
-
23.发明授权Suppressing power supply noise using data scrambling in double data rate memory systems 有权使用双数据速率存储器系统中的数据扰频抑制电源噪声公开(公告)号：US08503678B2
公开(公告)日：2013-08-06
申请号：US12646823
申请日：2009-12-23
IPC分类号： G06F21/00
CPC分类号： G06F7/584 , G06F2207/582
摘要： Embodiments are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.
摘要翻译： 实施例一般涉及使用双数据速率存储器系统中的数据加扰来抑制电源噪声的系统，方法和装置。 在一些实施例中，集成电路包括用于将数据发送到一个或多个存储器设备的发送数据路径。 发送数据路径可以包括加扰逻辑，以并行地生成与彼此不相关的N个伪随机输出。 输出数据和伪随机输出被输入到异或逻辑。 发送数据路径发送具有基本为白色频谱的XOR逻辑的输出。 描述和要求保护其他实施例。
-
24.发明授权Method and system for evaluating effects of signal phase difference on a memory system 有权用于评估信号相位差对存储器系统的影响的方法和系统公开(公告)号：US08331176B2
公开(公告)日：2012-12-11
申请号：US12628103
申请日：2009-11-30
申请人： Christopher P. Mozak , Kevin B. Moore , John V. Lovelace , Zale Theodore Schoenborn , Bryan L. Spry , Christopher E. Yunker
发明人： Christopher P. Mozak , Kevin B. Moore , John V. Lovelace , Zale Theodore Schoenborn , Bryan L. Spry , Christopher E. Yunker
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/023 , G11C29/028
摘要： In an embodiment, the effect of signal phase difference on a memory system is tested for various operating states. The various operating states may be represented as respective sample points on a plane defined by a range of values for a difference in signal phases and a range of values for another operating state parameter. In various embodiments, sample points for a round of crosstalk testing may include two sample points which are offset from the same reference point on the plane along different respective axes, where the axes are oblique to one another.
摘要翻译： 在一个实施例中，针对各种操作状态测试信号相位差对存储器系统的影响。 各种操作状态可以被表示为由用于信号相位差和用于另一操作状态参数的值的范围的值的范围所限定的平面上的相应采样点。 在各种实施例中，用于一轮串扰测试的采样点可以包括两个采样点，这两个采样点沿着不同相应轴的平面上的相同参考点偏移，其中轴彼此倾斜。
-
25.发明申请METHOD AND SYSTEM FOR EVALUATING EFFECTS OF SIGNAL PHASE DIFFERENCE ON A MEMORY SYSTEM 有权用于评估信号相位差对存储器系统的影响的方法和系统公开(公告)号：US20110131458A1
公开(公告)日：2011-06-02
申请号：US12628103
申请日：2009-11-30
申请人： Christopher P. Mozak , Kevin B. Moore , John V. Lovelace , Zale Theodore Schoenborn , Bryan L. Spry , Christopher E. Yunker
发明人： Christopher P. Mozak , Kevin B. Moore , John V. Lovelace , Zale Theodore Schoenborn , Bryan L. Spry , Christopher E. Yunker
CPC分类号： G11C29/02 , G11C29/023 , G11C29/028
摘要： In an embodiment, the effect of signal phase difference on a memory system is tested for various operating states. The various operating states may be represented as respective sample points on a plane defined by a range of values for a difference in signal phases and a range of values for another operating state parameter. In various embodiments, sample points for a round of crosstalk testing may include two sample points which are offset from the same reference point on the plane along different respective axes, where the axes are oblique to one another.
摘要翻译： 在一个实施例中，针对各种操作状态测试信号相位差对存储器系统的影响。 各种操作状态可以被表示为由用于信号相位差和用于另一操作状态参数的值的范围的值的范围所限定的平面上的相应采样点。 在各种实施例中，用于一轮串扰测试的采样点可以包括两个采样点，这两个采样点沿着不同相应轴的平面上的相同参考点偏移，其中轴彼此倾斜。
-
26.发明申请SUPPRESSING POWER SUPPLY NOISE USING DATA SCRAMBLING IN DOUBLE DATA RATE MEMORY SYSTEMS 有权使用双重数据速率记忆系统中的数据扫描来抑制电源噪声公开(公告)号：US20100153699A1
公开(公告)日：2010-06-17
申请号：US12646823
申请日：2009-12-23
CPC分类号： G06F7/584 , G06F2207/582
摘要： Embodiments are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.
摘要翻译： 实施例一般涉及使用双数据速率存储器系统中的数据加扰来抑制电源噪声的系统，方法和装置。 在一些实施例中，集成电路包括用于将数据发送到一个或多个存储器设备的发送数据路径。 发送数据路径可以包括加扰逻辑，以并行地生成与彼此不相关的N个伪随机输出。 输出数据和伪随机输出被输入到异或逻辑。 发送数据路径发送具有基本为白色频谱的XOR逻辑的输出。 描述和要求保护其他实施例。
-
公开(公告)号：US20180012886A1
公开(公告)日：2018-01-11
申请号：US15203296
申请日：2016-07-06
IPC分类号： H01L27/02
CPC分类号： H01L27/0281 , H01L27/0255 , H02H9/046
摘要： Some embodiments include apparatus and methods using a first transistor coupled between a node and a supply node, a second transistor coupled between the node and a ground node, an electrostatic discharge (ESD) protection unit including a diode coupled between the node and an additional node, and a transistor coupled between the additional node and the supply node.
-
28.发明授权公开(公告)号：US09536626B2
公开(公告)日：2017-01-03
申请号：US13763511
申请日：2013-02-08
CPC分类号： G11C11/4093 , G11C11/4074 , G11C11/4076 , G11C11/4096 , G11C29/06 , G11C29/56 , G11C2029/0401
摘要： A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.
摘要翻译： 内存子系统通过内存设备经验性地测试I / O的性能参数。 基于经验测试，存储器子系统可以设置特定于包含存储器子系统的系统的性能参数。 测试系统执行测试。 对于多个不同I / O电路参数的多个不同设置中的每一个，测试系统为每个I / O电路参数设置一个值，生成测试流量以用参数值对存储器件进行压力测试，并测量操作 裕量为I / O性能特点。 测试系统进一步执行搜索功能以确定每个I / O电路参数的值，在该参数下操作裕度满足最小阈值，并且至少一个I / O电路参数的性能提高。 内存子系统根据搜索功能设置I / O电路参数的运行时间值。
-
公开(公告)号：US09454329B2
公开(公告)日：2016-09-27
申请号：US13997399
申请日：2012-04-30
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0683 , G06F13/161 , G06F13/1684 , G06F13/1694 , G06F13/382 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, a system on a chip (SoC) includes a plurality of processor cores and a memory controller to control communication between the SoC and a memory coupled to the memory controller. The memory controller may be configured to send mirrored command and address signals to a first type of memory device and to send non-mirrored control and address signals to a second type of memory device. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，芯片上的系统（SoC）包括多个处理器核心和存储器控制器，用于控制SoC与耦合到存储器控制器的存储器之间的通信。 存储器控制器可以被配置为向第一类型的存储器件发送镜像命令和地址信号，并将非镜像控制和地址信号发送到第二类型的存储器件。 描述和要求保护其他实施例。
-
公开(公告)号：US09196384B2
公开(公告)日：2015-11-24
申请号：US13730429
申请日：2012-12-28
CPC分类号： G11C29/50 , G11C29/06 , G11C2029/5002
摘要： A memory subsystem can test a memory device in situ, testing the performance of parameters of operation the device in the system it is built into during production. Thus, the system can detect the specific values that will work for one or more operating parameters for the memory device in actual runtime. A test component embedded in the memory subsystem can perform a stress test and identify specific bits or lines of memory that experience failure under one or more stresses. The system can then map out the failed bits or lines to prevent the bits/lines from being used in runtime of the system.
摘要翻译： 存储器子系统可以原位测试存储器件，测试在生产过程中内置的系统中的器件的操作参数的性能。 因此，系统可以在实际的运行时间内检测可用于存储器件的一个或多个操作参数的特定值。 嵌入在存储器子系统中的测试组件可以执行压力测试并识别在一个或多个应力下经历故障的特定位或存储器行。 然后，系统可以映射失败的位或行，以防止在系统运行时使用位/线。
-
-
-
-
-
-
-
-
-
搜索结果
36 条记录 (耗时 0.025 秒)
