-
公开(公告)号：US20140095946A1
公开(公告)日：2014-04-03
申请号：US13631961
申请日：2012-09-29
IPC分类号： G11C29/08
CPC分类号： G11C29/08 , G11C29/56 , G11C2029/5602
摘要： A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test. The command identifies the test to implement, and the test engine generates one or more memory access transactions to implement the test on the memory device. The test engine passes the transactions to the memory controller, which can schedule the commands with its scheduler. Thus, the transactions cause deterministic behavior in the memory device because the transactions are executed as provided, while at the same time testing the actual operation of the device.
摘要翻译： 存储器子系统包括耦合到存储器控制器的测试引擎，其可以绕过存储器地址解码器来向存储器控制器提供存储器访问事务。 测试引擎接收到一个命令，使其生成事务以实现内存测试。 该命令标识要实现的测试，并且测试引擎生成一个或多个存储器访问事务以在存储器设备上实现测试。 测试引擎将事务传递到内存控制器，可以使用其调度程序来调度命令。 因此，交易在存储设备中引起确定性行为，因为交易按照提供的方式执行，同时测试设备的实际操作。
-
公开(公告)号：US08938573B2
公开(公告)日：2015-01-20
申请号：US13539417
申请日：2012-06-30
申请人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
发明人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
IPC分类号： G06F12/06 , G11C11/406 , G06F11/30
CPC分类号： G06F11/3037 , G06F11/004 , G06F11/3471 , G06F2201/81 , G06F2201/88 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.
摘要翻译： 系统监视对特定行存储器的数据访问，以确定是否存在行锤条件。 该系统可以监视所访问的存储行，以确定对任何行的访问次数是否超过与物理上与高访问行相邻的存储体上的数据损坏风险相关联的阈值。 基于监视，存储器控制器可以确定对行的访问次数是否超过阈值，并且指示访问计数达到阈值的行的地址信息。
-
公开(公告)号：US08819474B2
公开(公告)日：2014-08-26
申请号：US12417828
申请日：2009-04-03
IPC分类号： G06F1/12
CPC分类号： G06F13/4243 , G06F13/1689
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于存储器命令定时的主动训练的系统，方法和装置。 在一些实施例中，使用存储器模块和存储器控制器之间的主动反馈主动地训练CMD / CTL定时。 描述和要求保护其他实施例。
-
公开(公告)号：US20140157053A1
公开(公告)日：2014-06-05
申请号：US13706177
申请日：2012-12-05
IPC分类号： G11C29/10
CPC分类号： G11C29/02 , G11C29/022 , G11C29/06 , G11C29/36 , G11C29/50012 , G11C29/52
摘要： A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.
摘要翻译： 存储器子系统包括存储器控制器的测试信号发生器，其响应于存储器控制器接收测试事务而产生测试数据信号。 测试事务指示在相关联的存储设备上执行的一个或多个I / O操作。 测试信号发生器可以从各种不同的模式发生器产生数据信号。 存储器控制器调度器调度测试数据信号模式，并将其发送到存储器件。 然后，存储器件可以执行I / O操作来实现测试事务。 存储器控制器可以读取写入存储器件的特定地址的数据，并将回读数据与预期数据进行比较。 当回读数据和预期数据不匹配时，存储器控制器可以记录错误。 该错误可以包括错误的具体地址，特定数据和/或编码数据。
-
公开(公告)号：US09236110B2
公开(公告)日：2016-01-12
申请号：US13539415
申请日：2012-06-30
申请人： Kuljit S. Bains , John B. Halbert , Christopher P. Mozak , Theodore Z. Schoenborn , Zvika Greenfield
发明人： Kuljit S. Bains , John B. Halbert , Christopher P. Mozak , Theodore Z. Schoenborn , Zvika Greenfield
IPC分类号： G06F12/12 , G11C11/406
CPC分类号： G11C11/4091 , G06F3/0619 , G06F3/0659 , G06F3/0673 , G06F2212/7211 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.
-
公开(公告)号：US20140095947A1
公开(公告)日：2014-04-03
申请号：US13631962
申请日：2012-09-29
IPC分类号： G11C29/08
CPC分类号： G11C29/08 , G11C29/56 , G11C2029/5602
摘要： A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests. The test engine identifies a range of addresses through which to iterate a test sequence in response to receiving a software instruction indicating a test to perform. For each iteration of the test, the test engine, via the selected hardware, generates a memory access transaction, selects an address from the range, and sends the transaction to the memory controller. The memory controller schedules memory device commands in response to the transaction, which causes the memory device to execute operations to carry out the transaction.
摘要翻译： 存储器子系统包括耦合到存储器控制器的测试引擎，其可以绕过存储器地址解码器来向存储器控制器提供存储器访问事务。 测试引擎硬件可配置为不同的测试。 测试引擎识别响应于接收到指示要执行的测试的软件指令来迭代测试序列的地址范围。 对于测试的每次迭代，测试引擎通过选定的硬件生成内存访问事务，从范围中选择一个地址，并将事务发送到内存控制器。 存储器控制器响应于事务来调度存储器设备命令，这导致存储器件执行操作来执行事务。
-
公开(公告)号：US09009540B2
公开(公告)日：2015-04-14
申请号：US13706196
申请日：2012-12-05
申请人： Christopher P. Mozak , Theodore Z. Schoenborn , James M. Shehadi , David G. Ellis , Tomer Levy , Zvika Greenfield
发明人： Christopher P. Mozak , Theodore Z. Schoenborn , James M. Shehadi , David G. Ellis , Tomer Levy , Zvika Greenfield
IPC分类号： G06F11/00 , G06F11/263 , G11C29/02 , G11C29/06 , G11C29/52
CPC分类号： G06F11/263 , G11C29/02 , G11C29/025 , G11C29/06 , G11C29/52
摘要： A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.
摘要翻译： 存储器子系统包括耦合到存储器控制器和存储器件之间的命令总线的逻辑缓冲器。 逻辑缓冲区检测到存储器控制器将命令总线置于存储器控制器不使用有效的可执行存储器设备命令驱动命令总线的状态。 响应于检测到命令总线的状态，逻辑缓冲器产生信号模式，并且在存储器控制器的调度器之后在命令总线上注入信号模式以用信号模式驱动命令总线。
-
公开(公告)号：US20140006704A1
公开(公告)日：2014-01-02
申请号：US13539417
申请日：2012-06-30
申请人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
发明人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
IPC分类号： G06F11/30 , G11C11/406
CPC分类号： G06F11/3037 , G06F11/004 , G06F11/3471 , G06F2201/81 , G06F2201/88 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.
摘要翻译： 系统监视对特定行存储器的数据访问，以确定是否存在行锤条件。 该系统可以监视所访问的存储行，以确定对任何行的访问次数是否超过与物理上与高访问行相邻的存储体上的数据损坏风险相关联的阈值。 基于监视，存储器控制器可以确定对行的访问次数是否超过阈值，并且指示访问计数达到阈值的行的地址信息。
-
公开(公告)号：US20100257397A1
公开(公告)日：2010-10-07
申请号：US12417828
申请日：2009-04-03
CPC分类号： G06F13/4243 , G06F13/1689
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于存储器命令定时的主动训练的系统，方法和装置。 在一些实施例中，使用存储器模块和存储器控制器之间的主动反馈主动地训练CMD / CTL定时。 描述和要求保护其他实施例。
-
10.发明授权公开(公告)号：US09536626B2
公开(公告)日：2017-01-03
申请号：US13763511
申请日：2013-02-08
CPC分类号： G11C11/4093 , G11C11/4074 , G11C11/4076 , G11C11/4096 , G11C29/06 , G11C29/56 , G11C2029/0401
摘要： A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.
摘要翻译： 内存子系统通过内存设备经验性地测试I / O的性能参数。 基于经验测试，存储器子系统可以设置特定于包含存储器子系统的系统的性能参数。 测试系统执行测试。 对于多个不同I / O电路参数的多个不同设置中的每一个，测试系统为每个I / O电路参数设置一个值，生成测试流量以用参数值对存储器件进行压力测试，并测量操作 裕量为I / O性能特点。 测试系统进一步执行搜索功能以确定每个I / O电路参数的值，在该参数下操作裕度满足最小阈值，并且至少一个I / O电路参数的性能提高。 内存子系统根据搜索功能设置I / O电路参数的运行时间值。
-
-
-
-
-
-
-
-
-
搜索结果
51 条记录 (耗时 0.024 秒)
