公开(公告)号：US20080186769A1

公开(公告)日：2008-08-07

申请号：US11703115

申请日：2007-02-07

申请人： Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C11/34

CPC分类号： G11C7/18 ,  G11C7/02

摘要： A method for metal bit line arrangement is applied to a virtual ground array memory having memory cell blocks. Each memory cell block has memory cells and m metal bit lines, wherein m is a positive integer. The method includes the following steps. First, one of the memory cells is selected as a target memory cell. When the target memory cell is being read, the metal bit line electrically connected to a drain of the target memory cell is a drain metal bit line, and the metal bit line electrically connected to a source is a source metal bit line. Next, a classification of whether the other metal bit lines are charged up when the target memory cell is being read is made. Thereafter, the m metal bit lines are arranged such that charged up metal bit lines are not adjacent to the source metal bit line.

摘要翻译： 一种用于金属位线布置的方法被应用于具有存储单元块的虚拟地阵列存储器。 每个存储单元块具有存储单元和m个金属位线，其中m是正整数。 该方法包括以下步骤。 首先，选择一个存储单元作为目标存储器单元。 当读出目标存储单元时，与目标存储单元的漏极电连接的金属位线是漏极金属位线，与源极电连接的金属位线是源极金属位线。 接着，对目标存储单元进行读取时，分类其他金属位线是否被充电。 此后，m个金属位线布置成使得带电的金属位线不与源极金属位线相邻。

公开(公告)号：US20080123406A1

公开(公告)日：2008-05-29

申请号：US11555849

申请日：2006-11-02

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C2211/5621

摘要： A method for operating a multi-level cell (“MLC”) memory array of an integrated circuit (“IC”) programs first data into a first plurality of MLCs in the MLC memory array at a first programming level. Threshold voltages for the first plurality of MLCs are sensed, and an adjust code is set according to the threshold voltages. Second data is programmed into a second plurality of MLCs in the MLC memory array at a second programming level, the second plurality of MLCs having a program-verify value set according to the adjust code. In a further embodiment, a reference voltage for reading the second plurality of MLCs is set according to the adjust code.

摘要翻译： 用于操作集成电路（“IC”）的多级单元（“MLC”）存储器阵列的方法在第一编程级将第一数据编程到MLC存储器阵列中的第一多个MLC中。 感测第一多个MLC的阈值电压，并且根据阈值电压设置调整代码。 第二数据在第二编程级别被编程到MLC存储器阵列中的第二多个MLC中，第二多个MLC具有根据调整代码设置的程序验证值。 在另一实施例中，根据调整代码来设置用于读取第二多个MLC的参考电压。

公开(公告)号：US08924819B2

公开(公告)日：2014-12-30

申请号：US12358900

申请日：2009-01-23

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C29/04

CPC分类号： G06F11/1072 ,  G11C29/00 ,  G11C2029/0411

摘要： A method for operating a memory device is provided and includes the following steps. A first error correction code is generated according to user data. Then, the user data is written to the memory device. Moreover, the user data in the memory device is read, and a second error correction code is generated according to the read user data. Further, the first and the second error correction codes are written to the memory device.

摘要翻译： 提供了一种操作存储器件的方法，包括以下步骤。 根据用户数据生成第一个纠错码。 然后，将用户数据写入存储器件。 此外，读取存储器件中的用户数据，并根据读取的用户数据生成第二纠错码。 此外，将第一和第二纠错码写入存储器件。

公开(公告)号：US08743638B2

公开(公告)日：2014-06-03

申请号：US13564189

申请日：2012-08-01

申请人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

IPC分类号： G11C7/00

CPC分类号： G11C29/10 ,  G11C29/12005

摘要： A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.

摘要翻译： 提供了一种用于测试多芯片封装的方法和电路。 多芯片封装至少包括存储器芯片，并且存储器芯片包括多个存储器单元。 该方法包括对存储器单元执行正常读取操作，以检查从存储器单元读取的数据是否与存储器单元中的预置数据相同; 以及对所述存储器单元执行特殊读取操作，以检查从所述存储器单元读取的数据是否与期望值相同，其中所述期望值与存储在所述存储器单元中的数据无关。

公开(公告)号：US08363505B2

公开(公告)日：2013-01-29

申请号：US12785297

申请日：2010-05-21

申请人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Chun-Hsiung Hung

发明人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Chun-Hsiung Hung

IPC分类号： G11C8/08

CPC分类号： G11C8/08

摘要： A two transistor word line driver is disclosed. An example disclosed word line driver is simplified with common signals on the gates of the p-type and the n-type transistors. An example disclosed word line driver consumes less power by applying a negative voltage to a word line driver selected from multiple word line drivers.

摘要翻译： 公开了一种双晶体管字线驱动器。 所公开的公开的字线驱动器的示例通过p型和n型晶体管的栅极上的公共信号来简化。 所公开的字线驱动器的示例通过对从多个字线驱动器中选择的字线驱动器施加负电压而消耗较少的功率。

公开(公告)号：US08208332B2

公开(公告)日：2012-06-26

申请号：US12870313

申请日：2010-08-27

申请人： Wen-Chiao Ho ,  Ji-Yu Hung ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

发明人： Wen-Chiao Ho ,  Ji-Yu Hung ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

IPC分类号： G11C7/04

CPC分类号： G11C7/08 ,  G11C7/04

摘要： A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.

摘要翻译： 补偿电路包括比较器和仿真电路。 比较器具有第一端子和用于接收参考电压的第二端子。 仿真电路耦合到比较器的第一端。 仿真电路响应于温度，使得比较器在第一时间点输出读定时控制信号，或者在第二时间点输出读定时控制信号，第一时间点晚于第二时间点。

公开(公告)号：US08190984B2

公开(公告)日：2012-05-29

申请号：US13070008

申请日：2011-03-23

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Chun-Hsiung Hung ,  Kuen-Long Chang

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Chun-Hsiung Hung ,  Kuen-Long Chang

IPC分类号： G11C29/00 ,  G06F7/02 ,  H03M13/00

CPC分类号： H03M13/13 ,  G06F11/1068 ,  H03M13/03 ,  H03M13/3776

摘要： A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.

摘要翻译： 用于检查存储器的读取错误的方法包括以下步骤。 接收到第一个数据片段。 产生根据第一数据片段的第一计数索引，其中第一计数索引对应于第一数据片段中的一种二进制值的数量。 第一个数据片段被写入存储器。 第一数据片段作为第二数据片段从存储器读取。 根据第二数据片段生成第二计数索引。 将第一计数指数与第二计数指数进行比较。

公开(公告)号：US20110161750A1

公开(公告)日：2011-06-30

申请号：US13042910

申请日：2011-03-08

申请人： Chun-Hsiung Hung ,  Wen-Chiao Ho

发明人： Chun-Hsiung Hung ,  Wen-Chiao Ho

IPC分类号： G11C29/00 ,  G06F11/16

CPC分类号： G11C8/12 ,  G11C29/808

摘要： A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block.

摘要翻译： 预编码装置包括第一存储器电路，地址解码器和替代逻辑电路。 第一存储器电路包括多个存储器块，并且在东部包括替换块。 存储器块由多个相应的物理地址指向。 替换块由替换地址指向。 地址解码器解码输入地址以提供预代码地址。 替代逻辑电路查找地址映射表，其将物理地址中的缺陷物理地址映射到替换地址，以在预代码地址对应于缺陷物理地址时将前缀地址映射到替换地址。 替代逻辑电路相应地将代码前数据预编码到替换块。

公开(公告)号：US20100322018A1

公开(公告)日：2010-12-23

申请号：US12870313

申请日：2010-08-27

申请人： Wen-Chiao Ho ,  Ji-Yu Hung ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

发明人： Wen-Chiao Ho ,  Ji-Yu Hung ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

IPC分类号： G11C7/04

CPC分类号： G11C7/08 ,  G11C7/04

摘要： A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.

摘要翻译： 补偿电路包括比较器和仿真电路。 比较器具有第一端子和用于接收参考电压的第二端子。 仿真电路耦合到比较器的第一端。 仿真电路响应于温度，使得比较器在第一时间点输出读定时控制信号，或者在第二时间点输出读定时控制信号，第一时间点晚于第二时间点。

公开(公告)号：US20100124136A1

公开(公告)日：2010-05-20

申请号：US12271022

申请日：2008-11-14

申请人： Wen-Chiao Ho ,  Ji-Yu Hung ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

发明人： Wen-Chiao Ho ,  Ji-Yu Hung ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

IPC分类号： G11C7/04 ,  H03K3/02

CPC分类号： G11C7/08 ,  G11C7/04

摘要： A temperature compensation circuit includes a voltage generator, a comparator and an emulation cell array. The voltage generator provides a predetermined voltage and a reference voltage. The comparator has a first terminal for receiving the predetermined voltage, and a second terminal for receiving the reference voltage. The emulation cell array is coupled to the first terminal of the comparator. When a voltage of the first terminal of the comparator is discharged, via the emulation cell array, to be lower than the reference voltage, the comparator outputs a read timing control signal to control a sense amplifier to perform a sensing operation.

摘要翻译： 温度补偿电路包括电压发生器，比较器和仿真单元阵列。 电压发生器提供预定电压和参考电压。 比较器具有用于接收预定电压的第一端子和用于接收参考电压的第二端子。 仿真单元阵列耦合到比较器的第一端。 当比较器的第一端子的电压经由仿真单元阵列放电到低于参考电压时，比较器输出读取定时控制信号以控制读出放大器执行感测操作。