公开(公告)号：US08270223B2

公开(公告)日：2012-09-18

申请号：US12628710

申请日：2009-12-01

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines. A first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.

摘要翻译： 存储器件包括存储器扇区，其包括存储器扇区，一行选择晶体管和多个驱动器。 存储器扇区包括多个字线，每个字线耦合到多个存储器单元。 选择晶体管行选择存储器扇区，并将存储器扇区与存储器件中紧邻的存储器扇区分开。 多个驱动器中的每一个耦合到多个字线中的一个。 驱动器中的第一个被耦合到字线中的第一个以接收第一控制信号以传导第一字线和电压源，并且第二驱动器耦合到第二个字线 以接收第二控制信号以将第二字线与电压源断开。

公开(公告)号：US20110085380A1

公开(公告)日：2011-04-14

申请号：US12970222

申请日：2010-12-16

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.

摘要翻译： 一种对存储器进行编程的方法，其中所述存储器包括具有多个多电平单元的许多存储区域。 每个存储器区域包括第一位线，第二位线，数据缓冲器和保护单元。 耦合到第一和第二位线的保护单元和数据缓冲器防止编程错误发生。 在编程方法的实施例中，对应的数据分别输入到数据缓冲器。 对应于第n阶段的数据被编程到目标多级单元中。 修改对应于第（n + 1）个相位的数据，以使对应于第（n + 1）相的数据与对应于第n相的数据相同，如果目标多电平单元通过编程验证处理 根据第n个编程验证电压。 重复上述步骤直到n等于最大值，n为正整数。

公开(公告)号：US20100054045A1

公开(公告)日：2010-03-04

申请号：US12204009

申请日：2008-09-04

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C7/00

CPC分类号： G11C16/24 ,  G11C16/26

摘要： A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line.

摘要翻译： 存储器包括多个存储区域，每个存储器区域包括目标存储器单元，源极线，位线和读取控制电路。 源极线耦合到目标存储器单元的第一端子。 位线耦合到目标存储器单元的第二端子。 读取控制电路用于选择性地向源极线施加工作电压。

公开(公告)号：US20090201060A1

公开(公告)日：2009-08-13

申请号：US12027285

申请日：2008-02-07

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： H03L7/00

CPC分类号： H03K5/135 ,  H03K5/06 ,  H03K2005/00195

摘要： A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.

摘要翻译： 提供了应用在SMD块中的时钟同步电路。 时钟同步电路包括多个时钟同步单元级。 时钟同步电路可以通过使用时钟同步单元的每一级中的前向延迟单元，反射镜控制单元或后向延迟单元的新颖的电路设计来实现时钟同步的目的，或者通过使用短脉冲发生电路来产生 用于触发前级延迟单元各级的输出时钟的短脉冲。

公开(公告)号：US20080304337A1

公开(公告)日：2008-12-11

申请号：US12174115

申请日：2008-07-16

申请人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

IPC分类号： G11C7/00

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C11/5671

摘要： A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2n bits, n is a positive integer. The method for accessing memory includes the following steps: Firstly, threshold voltages of the storage are defined into 2n level respectively, wherein each of the 2n level corresponds to a storage status of n bits, and most significant bits of the storage statuses which level 0 to level 2n/2−1 correspond to are different from most significant bits of the storage statuses which level 2n/2 to level 2n−1 correspond to. Next, a target data is divided into n portions and the divided target data is written into n temporary memories respectively. Then, n bits of the target data are written into the multi-level cell. Each of the n bits data is collected from each of the n temporary memories.

摘要翻译： 提供了访问存储器的方法。 存储器包括许多多级单元，每个单元具有至少一个能存储2n位的存储器，n是正整数。 访问存储器的方法包括以下步骤：首先，将存储器的阈值电压分别定义为2n级，其中2n级中的每一级对应于n位的存储状态，存储状态的最高有效位为0级 等级2n / 2-1对应于不同于2n / 2到2n-1级对应的存储状态的最高有效位。 接下来，目标数据被分成n个部分，分割的目标数据被分别写入n个临时存储器。 然后，将目标数据的n位写入多级单元。 从n个临时存储器中的每一个收集n位数据中的每一个。

公开(公告)号：US08176373B2

公开(公告)日：2012-05-08

申请号：US13042910

申请日：2011-03-08

申请人： Chun-Hsiung Hung ,  Wen-Chiao Ho

发明人： Chun-Hsiung Hung ,  Wen-Chiao Ho

IPC分类号： G11C29/00

CPC分类号： G11C8/12 ,  G11C29/808

摘要： A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block.

摘要翻译： 预编码装置包括第一存储器电路，地址解码器和替代逻辑电路。 第一存储器电路包括多个存储器块，并且在东部包括替换块。 存储器块由多个相应的物理地址指向。 替换块由替换地址指向。 地址解码器解码输入地址以提供预代码地址。 替代逻辑电路查找地址映射表，其将物理地址中的缺陷物理地址映射到替换地址，以在预代码地址对应于缺陷物理地址时将前缀地址映射到替换地址。 替代逻辑电路相应地将代码前数据预编码到替换块。

公开(公告)号：US07965551B2

公开(公告)日：2011-06-21

申请号：US11703115

申请日：2007-02-07

申请人： Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C11/34

CPC分类号： G11C7/18 ,  G11C7/02

摘要： A method for metal bit line arrangement is applied to a virtual ground array memory having memory cell blocks. Each memory cell block has memory cells and m metal bit lines, wherein m is a positive integer. The method includes the following steps. First, one of the memory cells is selected as a target memory cell. When the target memory cell is being read, the metal bit line electrically connected to a drain of the target memory cell is a drain metal bit line, and the metal bit line electrically connected to a source is a source metal bit line. Next, a classification of whether the other metal bit lines are charged up when the target memory cell is being read is made. Thereafter, the m metal bit lines are arranged such that charged up metal bit lines are not adjacent to the source metal bit line.

摘要翻译： 一种用于金属位线布置的方法被应用于具有存储单元块的虚拟地阵列存储器。 每个存储单元块具有存储单元和m个金属位线，其中m是正整数。 该方法包括以下步骤。 首先，选择一个存储单元作为目标存储单元。 当读出目标存储单元时，与目标存储单元的漏极电连接的金属位线是漏极金属位线，与源极电连接的金属位线是源极金属位线。 接着，对目标存储单元进行读取时，分类其他金属位线是否被充电。 此后，m个金属位线布置成使得带电的金属位线不与源极金属位线相邻。

公开(公告)号：US07652512B2

公开(公告)日：2010-01-26

申请号：US12027285

申请日：2008-02-07

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： H03L7/00

CPC分类号： H03K5/135 ,  H03K5/06 ,  H03K2005/00195

摘要： A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.

摘要翻译： 提供了应用在SMD块中的时钟同步电路。 时钟同步电路包括多个时钟同步单元级。 时钟同步电路可以通过使用时钟同步单元的每一级中的前向延迟单元，反射镜控制单元或后向延迟单元的新颖的电路设计来实现时钟同步的目的，或者通过使用短脉冲发生电路来产生 用于触发前级延迟单元各级的输出时钟的短脉冲。

公开(公告)号：US07649772B2

公开(公告)日：2010-01-19

申请号：US11779951

申请日：2007-07-19

申请人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Wen-Chiao Ho

发明人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Wen-Chiao Ho

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475

摘要： A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data.

摘要翻译： 一种用于编程存储器的方法，包括多个具有左半单元和右半单元的多级单元，包括以下步骤。 首先，提供与要存储的2n组数据对应的目标地址，其中n是正整数。 接下来，基于编程循环中的目标地址，将2n组数据顺序地编程到多电平单元中，使得存储在左半单元中的数据和存储在右半单元中的数据来自不同的组 2n组数据。

公开(公告)号：US07639533B2

公开(公告)日：2009-12-29

申请号：US12028405

申请日：2008-02-08

申请人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C11/03

CPC分类号： G11C11/5628 ,  G11C2211/5621

摘要： A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied to the first memory cell upon reaching the predetermined threshold voltage is recorded. A second memory cell is programmed to a second threshold state by applying an initial bias voltage to the second memory cell which is function of the recorded bias voltage.

摘要翻译： 用于编程本文所述的多个多电平存储器单元的方法包括迭代地改变施加到第一存储器单元的偏置电压，以将第一存储器单元编程为第一阈值状态，以及检测第一单元何时达到预定阈值电压。 记录在达到预定阈值电压时施加到第一存储单元的偏置电压。 通过对作为记录的偏置电压的函数的第二存储器单元施加初始偏置电压将第二存储单元编程为第二阈值状态。