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公开(公告)号：US07652512B2
公开(公告)日：2010-01-26
申请号：US12027285
申请日：2008-02-07
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , H03K5/06 , H03K2005/00195
摘要： A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.
摘要翻译： 提供了应用在SMD块中的时钟同步电路。 时钟同步电路包括多个时钟同步单元级。 时钟同步电路可以通过使用时钟同步单元的每一级中的前向延迟单元，反射镜控制单元或后向延迟单元的新颖的电路设计来实现时钟同步的目的，或者通过使用短脉冲发生电路来产生 用于触发前级延迟单元各级的输出时钟的短脉冲。
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公开(公告)号：US07639533B2
公开(公告)日：2009-12-29
申请号：US12028405
申请日：2008-02-08
IPC分类号： G11C11/03
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied to the first memory cell upon reaching the predetermined threshold voltage is recorded. A second memory cell is programmed to a second threshold state by applying an initial bias voltage to the second memory cell which is function of the recorded bias voltage.
摘要翻译： 用于编程本文所述的多个多电平存储器单元的方法包括迭代地改变施加到第一存储器单元的偏置电压，以将第一存储器单元编程为第一阈值状态，以及检测第一单元何时达到预定阈值电压。 记录在达到预定阈值电压时施加到第一存储单元的偏置电压。 通过对作为记录的偏置电压的函数的第二存储器单元施加初始偏置电压将第二存储单元编程为第二阈值状态。
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公开(公告)号：US20090059668A1
公开(公告)日：2009-03-05
申请号：US11892979
申请日：2007-08-29
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/0491
摘要： A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. Next, the second cell is read and the data is recorded in a register. Then, the target cell is programmed. Next, a program verifying operation is performed on the second cell. Afterwards, the data recorded in the register is programmed back to the second cell when the program verifying operation performed on the second cell fails.
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公开(公告)号：US07499335B2
公开(公告)日：2009-03-03
申请号：US11703916
申请日：2007-02-07
IPC分类号： G11C16/04
CPC分类号： G11C11/5635 , G11C16/107 , G11C16/16 , G11C16/3459 , G11C2211/5621
摘要： A method for performing an erase operation is disclosed in a non-volatile memory having a plurality of memory cells. At least one memory cell is programmed having a threshold voltage level in a first region before programming, and after programming the memory cell has a threshold voltage level in a second region, wherein the second region is higher in threshold voltage than the fist region. The erasing operation implements a programming of memory bits that can inject negative charge carriers or electrons into a memory cell instead of using the conventional technique of injecting hot holes into the memory cell. This can avoid room temperature drift and charge loss caused by hot hole injection.
摘要翻译： 在具有多个存储单元的非易失性存储器中公开了一种用于执行擦除操作的方法。 至少一个存储器单元被编程为在编程之前具有第一区域中的阈值电压电平，并且在编程之后，存储器单元在第二区域中具有阈值电压电平，其中第二区域的阈值电压高于第一区域。 擦除操作实现了可以将负电荷载流子或电子注入到存储单元中的存储器位的编程，而不是使用将热空穴注入存储单元的常规技术。 这可以避免热空穴注入引起的室温漂移和电荷损失。
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公开(公告)号：US08190984B2
公开(公告)日：2012-05-29
申请号：US13070008
申请日：2011-03-23
CPC分类号： H03M13/13 , G06F11/1068 , H03M13/03 , H03M13/3776
摘要： A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.
摘要翻译： 用于检查存储器的读取错误的方法包括以下步骤。 接收到第一个数据片段。 产生根据第一数据片段的第一计数索引，其中第一计数索引对应于第一数据片段中的一种二进制值的数量。 第一个数据片段被写入存储器。 第一数据片段作为第二数据片段从存储器读取。 根据第二数据片段生成第二计数索引。 将第一计数指数与第二计数指数进行比较。
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公开(公告)号：US07619925B2
公开(公告)日：2009-11-17
申请号：US11892979
申请日：2007-08-29
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/0491
摘要： A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. Next, the second cell is read and the data is recorded in a register. Then, the target cell is programmed. Next, a program verifying operation is performed on the second cell. Afterwards, the data recorded in the register is programmed back to the second cell when the program verifying operation performed on the second cell fails.
摘要翻译： 一种用于对包括第一单元和与第一单元相邻的第二单元的虚拟地阵列存储器进行编程的方法包括以下步骤。 首先，选择第一小区作为目标小区，其中第二小区已被编程为具有数据。 接下来，读取第二单元，并将数据记录在寄存器中。 然后，对目标单元进行编程。 接下来，对第二小区执行程序验证操作。 之后，当对第二单元执行的程序验证操作失败时，将记录在寄存器中的数据编程回第二单元。
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公开(公告)号：US07580302B2
公开(公告)日：2009-08-25
申请号：US11551974
申请日：2006-10-23
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/5642 , G11C16/04 , G11C29/50004 , G11C2211/5634 , G11C2211/5644
摘要： A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.
摘要翻译： 用于确定存储器阵列中的读取电压余量的方法将从存储器阵列读取的数据产生的读取和编码与从加载数据生成的预期总和进行比较。 读取电压（Vt）是步进的，将读取的和码与预期的和码进行比较，以确定提供匹配和码的Vt范围。 当Vt跨过其范围时，以并行方式确定多个读取电压余量（即，MLC存储器阵列的多个编程电平之间的读取电压余量）。
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公开(公告)号：US20090154233A1
公开(公告)日：2009-06-18
申请号：US11946893
申请日：2007-11-29
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line is coupled to a second column of the multi-level cells. The data buffer is coupled to the first bit line and the second bit line and for storing data to be programmed into the multi-level cells. The protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error from occurring.
摘要翻译： 存储器包括许多存储器区域。 存储区具有多个多级单元。 每个存储器区域包括第一位线，第二位线，数据缓冲器和保护单元。 第一位线耦合到多级单元的第一列。 第二位线耦合到多电平单元的第二列。 数据缓冲器耦合到第一位线和第二位线，并用于存储要编程到多电平单元中的数据。 保护单元耦合到第一位线，第二位线和数据缓冲器，并且用于防止发生编程错误。
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公开(公告)号：US20080186780A1
公开(公告)日：2008-08-07
申请号：US11703916
申请日：2007-02-07
IPC分类号： G11C16/14
CPC分类号： G11C11/5635 , G11C16/107 , G11C16/16 , G11C16/3459 , G11C2211/5621
摘要： A method for performing an erase operation is disclosed in a non-volatile memory having a plurality of memory cells. At least one memory cell is programmed having a threshold voltage level in a first region before programming, and after programming the memory cell has a threshold voltage level in a second region, wherein the second region is higher in threshold voltage than the fist region. The erasing operation implements a programming of memory bits that can inject negative charge carriers or electrons into a memory cell instead of using the conventional technique of injecting hot holes into the memory cell. This can avoid room temperature drift and charge loss caused by hot hole injection.
摘要翻译： 在具有多个存储单元的非易失性存储器中公开了一种用于执行擦除操作的方法。 至少一个存储器单元被编程为在编程之前具有第一区域中的阈值电压电平，并且在编程之后，存储器单元在第二区域中具有阈值电压电平，其中第二区域的阈值电压高于第一区域。 擦除操作实现了可以将负电荷载流子或电子注入到存储单元中的存储器位的编程，而不是使用将热空穴注入存储单元的常规技术。 这可以避免热空穴注入引起的室温漂移和电荷损失。
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公开(公告)号：US20080094891A1
公开(公告)日：2008-04-24
申请号：US11551974
申请日：2006-10-23
CPC分类号： G11C29/50 , G11C11/5642 , G11C16/04 , G11C29/50004 , G11C2211/5634 , G11C2211/5644
摘要： A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.
摘要翻译： 用于确定存储器阵列中的读取电压余量的方法将从存储器阵列读取的数据产生的读取和编码与从加载数据生成的预期总和进行比较。 读取电压（Vt）是步进的，将读取的和码与预期的和码进行比较，以确定提供匹配和码的Vt范围。 当Vt跨过其范围时，以并行方式确定多个读取电压余量（即，MLC存储器阵列的多个编程电平之间的读取电压余量）。
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