公开(公告)号：US08255837B2

公开(公告)日：2012-08-28

申请号：US12616970

申请日：2009-11-12

Applicant: Lee-Chung Lu ,  Yi-Kan Cheng ,  Yuan-Te Hou ,  Yung-Chin Hou ,  Li-Chun Tien

Inventor： Lee-Chung Lu ,  Yi-Kan Cheng ,  Yuan-Te Hou ,  Yung-Chin Hou ,  Li-Chun Tien

IPC: G06F17/50

CPC classification number: G03F1/70 ,  G03F1/00

Abstract: A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.

Abstract translation: 设计用于芯片布局的双重图案掩模组的方法包括设计标准单元。 在每个标准单元中，所有左边界图案被分配有第一指示符和第二指示符中的一个，并且所有右边图案都被分配有第一指示符和第二指示符中的另外一个。 该方法还包括将标准单元放置在芯片布局的一行中。 从行中的一个标准单元开始，标记单元的指示符更改在整行中传播。 具有第一指示符的标准单元中的所有图案被转移到双图案掩模组的第一掩模。 具有第二指示器的标准单元中的所有图案被转移到双重图案掩模组的第二掩模。

公开(公告)号：US08239806B2

公开(公告)日：2012-08-07

申请号：US12649979

申请日：2009-12-30

Applicant: Huang-Yu Chen ,  Yuan-Te Hou ,  Gwan Sin Chang ,  Wen-Ju Yang ,  Zhe-Wei Jiang ,  Yi-Kan Cheng ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Gwan Sin Chang ,  Wen-Ju Yang ,  Zhe-Wei Jiang ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.

Abstract translation: 一种方法包括接收要包括在IC布局中的多个电路部件的标识。 生成表示连接两个电路部件的第一图案的数据。 第一图案具有多个片段。 至少两个片段具有彼此垂直的纵向方向。 保留与至少两个段中的至少一个相邻的至少一个无图案区域。 生成表示在第一图案附近的一个或多个附加图案的数据。 在无模式区域中没有形成附加图案。 第一种图案和附加图案形成双重图案化顺应的图案集合。 将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

公开(公告)号：US08136168B2

公开(公告)日：2012-03-13

申请号：US11687384

申请日：2007-03-16

Applicant: Yi-Kan Cheng ,  Gwan Sin Chang ,  Jill Liu ,  Hsiao-Shu Chiao

Inventor： Yi-Kan Cheng ,  Gwan Sin Chang ,  Jill Liu ,  Hsiao-Shu Chiao

IPC: H04L29/06

CPC classification number: H04L9/00 ,  G06F21/72 ,  H04L2209/12

Abstract: An encryption and decryption interface for integrated circuit (IC) design with design-for-manufacturing (DFM). The interface includes a decryption module embedded in an IC design tool; an encrypted DFM data provided to an IC designer authorized for utilizing the encrypted DFM data; and a private key provided to the IC designer for decrypting the encrypted DFM data in the IC design tool.

Abstract translation: 用于制造设计（DFM）的集成电路（IC）设计的加密和解密接口。 该接口包括嵌入在IC设计工具中的解密模块; 提供给被授权使用加密的DFM数据的IC设计的加密的DFM数据; 以及提供给IC设计者的用于解密IC设计工具中加密的DFM数据的私钥。

公开(公告)号：US20110072405A1

公开(公告)日：2011-03-24

申请号：US12831982

申请日：2010-07-07

Applicant: Huang-Yu Chen ,  Ho Che Yu ,  Chung-Hsing Wang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Ho Che Yu ,  Chung-Hsing Wang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L27/0207

Abstract: In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.

Abstract translation: 在形成集成电路的方法中，提供包括第一知识产权（IP）的芯片表示的布局。 生成与第一个IP重叠并从第一个IP边缘延伸出来的切割线。 切割线将芯片表示划分成多个电路区域。 多个电路区域相对于第一IP的位置向外偏移以产生空间。 第一个IP被吹入空间，产生一个IP地址。 然后执行直接收缩。

公开(公告)号：US07725861B2

公开(公告)日：2010-05-25

申请号：US11689197

申请日：2007-03-21

Applicant: Yi-Kan Cheng ,  Chih-Ming Lai ,  Ru-Gun Liu

Inventor： Yi-Kan Cheng ,  Chih-Ming Lai ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Efficient and cost-effective systems and methods for detecting and correcting hot spots of semiconductor devices are disclosed. In one aspect, a method for creating a layout from a circuit design is described. The method includes applying a first set of hot spot conditions to a global route to produce a detailed route; applying a second set of hot spot conditions to the detailed route to produce a post-detailed route; and applying a third set of hot spot conditions to the post-detailed route to produce the layout. In another aspect, a method includes providing a circuit design; applying a first hot spot filter to a global routing of the circuit design to produce a detailed route; applying a less pessimistic, second hot spot filter to the detailed route to produce a post-detailed route; and performing a rip-up and reroute of the post-detailed route to produce a final layout.

Abstract translation: 公开了用于检测和校正半导体器件的热点的高效且成本有效的系统和方法。 在一个方面，描述了一种用于从电路设计创建布局的方法。 该方法包括将第一组热点条件应用于全局路由以产生详细路由; 将第二组热点条件应用于详细路线以产生后详细路线; 以及将第三组热点条件应用于后详细路线以产生布局。 另一方面，一种方法包括提供电路设计; 将第一热点滤波器应用于电路设计的全局路由以产生详细的路由; 在详细的路线上应用较不悲观的第二热点过滤器，以产生详细的路线; 并执行后期详细路线的撤销和重新路线以产生最终布局。

公开(公告)号：US08907441B2

公开(公告)日：2014-12-09

申请号：US12702885

申请日：2010-02-09

Applicant: Huang-Yu Chen ,  Yuan-Te Hou ,  Fung Song Lee ,  Wen-Ju Yang ,  Gwan Sin Chang ,  Yi-Kan Cheng ,  Li-Chun Tien ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Fung Song Lee ,  Wen-Ju Yang ,  Gwan Sin Chang ,  Yi-Kan Cheng ,  Li-Chun Tien ,  Lee-Chung Lu

IPC: H01L21/70 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

CPC classification number: G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

Abstract translation: 半导体芯片包括一行单元，其中每个单元包括VDD线和VSS线。 单元的所有VDD线连接为单个VDD线，并且单元的所有VSS线都以单个VSS线连接。 在单元格行中不存在具有偶数个G0路径的双重图案化完整轨迹，或者在单元行中不存在具有奇数个G0路径的双图案化完整轨迹。

公开(公告)号：US08775977B2

公开(公告)日：2014-07-08

申请号：US13027520

申请日：2011-02-15

Applicant: Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

Inventor： Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC: G06F17/50

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.

Abstract translation: 提供了一种用于评估半导体器件级的设计布局并通过分解设计布局来确定和指定由不同光掩模形成的设计布局的不同特征的系统和方法。 这些特征由标记指定，该标记将各种器件特征与将在其上形成的多个光掩模相关联，然后使用双重图案化光刻DPL技术在半导体器件层面上产生。 标记是在设备级完成的，并被包括在由设计公司提供给光掩模铸造厂的电子文件中。 除了正在分解的设计布局的重叠和关键维度考虑之外，在确定和标记各种设备时，还考虑了各种其他设备标准，设计标准处理标准及其相关性以及设备环境和其他设备层 特征。

公开(公告)号：US08621409B2

公开(公告)日：2013-12-31

申请号：US13459288

申请日：2012-04-30

Applicant: Hui Yu Lee ,  Feng Wei Kuo ,  Ching-Shun Yang ,  Yi-Kan Cheng ,  Jui-Feng Kuan

Inventor： Hui Yu Lee ,  Feng Wei Kuo ,  Ching-Shun Yang ,  Yi-Kan Cheng ,  Jui-Feng Kuan

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5081

Abstract: A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.

Abstract translation: 一种方法包括从半导体电路的第一布局提取第一网表并基于第一网表估计与布局有关的效果数据。 基于使用电子设计自动化工具的第一网表执行半导体电路的第一仿真，并且基于使用电子设计自动化工具的电路示意图来执行半导体电路的第二仿真。 计算至少一个与布局相关的效果的重量和灵敏度，并且基于重量和灵敏度来调整半导体电路的第一布局以提供半导体电路的第二布局。 第二布局存储在非瞬态存储介质中。

公开(公告)号：US08601416B2

公开(公告)日：2013-12-03

申请号：US13535709

申请日：2012-06-28

Applicant: Chin-Cheng Kuo ,  Wei-Yi Hu ,  Jui-Feng Kuan ,  Yi-Kan Cheng

Inventor： Chin-Cheng Kuo ,  Wei-Yi Hu ,  Jui-Feng Kuan ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/10

Abstract: A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.

Abstract translation: 一种方法包括（a）产生一组样本，每个样本表示相应的一组半导体制造工艺变化值; （b）基于与每个样本相对应的半导体制造工艺变化值的集合的概率来选择该组样本的第一子集; （c）在不执行蒙特卡罗模拟的情况下，基于所述一组样本和所述第一子集的相对大小来估计半导体产品的屈服度量; 以及（d）如果估计的收益率测量低于规格收益率值，则输出设计修改适当的指示。

公开(公告)号：US08448100B1

公开(公告)日：2013-05-21

申请号：US13444158

申请日：2012-04-11

Applicant: Hung Lung Lin ,  Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Yi-Chuin Tsai ,  Yuan-Te Hou ,  Chung-Hsing Wang

Inventor： Hung Lung Lin ,  Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Yi-Chuin Tsai ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G03F1/70

Abstract: A computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons. A special-purpose computer is configured to perform the steps of: analyzing in the initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; and causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications.

Abstract translation: 计算机实现的系统包括：编码有表示具有多个多边形的集成电路图案层的初始布局的数据的有形的，非暂时性的计算机可读存储介质。 专用计算机被配置为执行以下步骤：在具有多个多边形的集成电路图案层的初始布局中进行分析，以便在初始布局中识别多个多图案化冲突循环; 在计算机中构建表示每个识别的多图案化冲突周期的相应的多图案化冲突循环图; 根据围绕该多图案化冲突循环图的其他多图案化冲突循环图的数量，在计算机中分类每个识别的多图案化冲突循环图; 并且使得显示装置根据它们各自的分类图形地显示多个多图案化冲突循环图。