公开(公告)号：US08775977B2

公开(公告)日：2014-07-08

申请号：US13027520

申请日：2011-02-15

申请人： Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

发明人： Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  G03F7/70433 ,  G03F7/70466

摘要： Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.

摘要翻译： 提供了一种用于评估半导体器件级的设计布局并通过分解设计布局来确定和指定由不同光掩模形成的设计布局的不同特征的系统和方法。 这些特征由标记指定，该标记将各种器件特征与将在其上形成的多个光掩模相关联，然后使用双重图案化光刻DPL技术在半导体器件层面上产生。 标记是在设备级完成的，并被包括在由设计公司提供给光掩模铸造厂的电子文件中。 除了正在分解的设计布局的重叠和关键维度考虑之外，在确定和标记各种设备时，还考虑了各种其他设备标准，设计标准处理标准及其相关性以及设备环境和其他设备层 特征。

公开(公告)号：US08468470B2

公开(公告)日：2013-06-18

申请号：US13238127

申请日：2011-09-21

申请人： Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

发明人： Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G03F1/70

摘要： A method comprises (a) receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving at least one identification of a subset of the plurality of polygons that are to be formed in the DPT-layer using the same photomask as each other; (c) constructing a graph of the subset of the plurality of polygons and any intervening polygons of the plurality of polygons, where the subset of the plurality of polygons are represented in the graph by a single node, the graph including connections connecting adjacent ones of the polygons in the graph that are positioned within a threshold distance of each other; and (d) identifying a multi-patterning conflict if any subset of the connections form an odd loop.

摘要翻译： 一种方法包括（a）接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据，该布局包括通过多图案化工艺在DPT层中形成的多个多边形; （b）使用彼此相同的光掩模来接收要在DPT层中形成的多个多边形的子集的至少一个标识; （c）构造所述多个多边形的子集的图形和所述多个多边形中的任何中间多边形，其中所述多个多边形的所述子集由所述图形中的单个节点表示，所述图包括连接相邻的多边形的连接 图中的多边形位于彼此的阈值距离内; 和（d）如果连接的任何子集形成奇数循环，则识别多图案化冲突。

公开(公告)号：US08473873B2

公开(公告)日：2013-06-25

申请号：US13224486

申请日：2011-09-02

申请人： Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

发明人： Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G03F1/70

摘要： A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

摘要翻译： 一种方法包括接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据。 该布局包括通过多图案化工艺在DPT层中形成的多个多边形。 分别使用第一和第二光掩模形成的多个多边形中的第一和第二多边形。 识别沿着连接第一多边形到第二多边形的第一路径以及沿着第一路径的相邻多边形之间的分隔区域的任何中间多边形。 分离器区域具有小于形成在第一光掩模上的多边形之间的最小阈值距离的尺寸。 计数分离器区域。 在将所述多个多边形中的所有剩余的多边形分配给第一或第二掩模之前，如果分离器区域的计数是偶数，则识别多图案化冲突。

公开(公告)号：US08448100B1

公开(公告)日：2013-05-21

申请号：US13444158

申请日：2012-04-11

申请人： Hung Lung Lin ,  Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Yi-Chuin Tsai ,  Yuan-Te Hou ,  Chung-Hsing Wang

发明人： Hung Lung Lin ,  Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Yi-Chuin Tsai ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC分类号： G06F17/50

CPC分类号： G03F1/70

摘要： A computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons. A special-purpose computer is configured to perform the steps of: analyzing in the initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; and causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications.

摘要翻译： 计算机实现的系统包括：编码有表示具有多个多边形的集成电路图案层的初始布局的数据的有形的，非暂时性的计算机可读存储介质。 专用计算机被配置为执行以下步骤：在具有多个多边形的集成电路图案层的初始布局中进行分析，以便在初始布局中识别多个多图案化冲突循环; 在计算机中构建表示每个识别的多图案化冲突周期的相应的多图案化冲突循环图; 根据围绕该多图案化冲突循环图的其他多图案化冲突循环图的数量，在计算机中分类每个识别的多图案化冲突循环图; 并且使得显示装置根据它们各自的分类图形地显示多个多图案化冲突循环图。

公开(公告)号：US08434043B1

公开(公告)日：2013-04-30

申请号：US13480847

申请日：2012-05-25

申请人： Chin-Chang Hsu ,  HungLung Lin ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

发明人： Chin-Chang Hsu ,  HungLung Lin ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： The present disclosure relates to a method and apparatus for identifying pre-coloring violations and for providing hints and/or warnings to a designer to eliminate the pre-coloring violations. In some embodiments, the method is performed by identifying G0-spaces within a double patterning technology (DPT) layer, of an integrated chip (IC) layout, having a plurality of pre-colored shapes. Violation paths extending between the pre-colored shapes are identified based upon the G0-spaces. Good paths (i.e., paths that will not cause a violation) and bad paths (i.e., paths that will cause a violation) between the pre-colored shapes are also identified. Hints and/or warnings are generated based upon the identified good and bad paths, wherein the hints and/or warnings provide guidance to eliminate the violation paths and develop a violation free IC layout.

摘要翻译： 本公开涉及一种用于识别预着色违规的方法和装置，并且用于向设计者提供提示和/或警告以消除预着色违规。 在一些实施例中，该方法通过识别具有多个预着色形状的集成芯片（IC）布局的双图案形成技术（DPT）层内的G0空间来执行。 基于G0空格识别在预色图案之间延伸的违规路径。 还识别出良好路径（即，不会引起违规的路径）和不良路径（即将导致违规的路径）。 提示和/或警告是基于所识别的好路径和不良路径生成的，其中提示和/或警告提供指导以消除违规路径并开发无违规IC布局。

公开(公告)号：US08726200B2

公开(公告)日：2014-05-13

申请号：US13303374

申请日：2011-11-23

申请人： Chung-Min Fu ,  Yung-Fong Lu ,  Wen-Ju Yang ,  Chin-Chang Hsu

发明人： Chung-Min Fu ,  Yung-Fong Lu ,  Wen-Ju Yang ,  Chin-Chang Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/70

摘要： Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

摘要翻译： 装置包括用于存储具有至少一个模板的模板库的机器可读存储介质。 该模板将包括通过多图案化IC的单层而形成的至少一个图案的第一布局图示。 该图案具有使用多个分别不同的光掩模形成的多个部分。 第一布局表示包括识别每个部分将要位于哪个光掩模上的数据。 电子设计自动化（EDA）工具包括被配置为接收电路的至少一部分的硬件描述语言表示并且生成具有多个多边形的电路的一部分的第二布局表示的处理器。 EDA工具具有匹配模块，其识别并输出多个部分中的一个或多个部分是否匹配多个多边形的子集的指示。

公开(公告)号：USD664105S1

公开(公告)日：2012-07-24

申请号：US29398400

申请日：2011-07-29

申请人： Chin-Chang Hsu

设计人： Chin-Chang Hsu

公开(公告)号：US07985003B2

公开(公告)日：2011-07-26

申请号：US12197723

申请日：2008-08-25

申请人： Wen-Lung Su ,  Chin-Chang Hsu ,  Hsuan-Chi Liu

发明人： Wen-Lung Su ,  Chin-Chang Hsu ,  Hsuan-Chi Liu

IPC分类号： F21S4/00 ,  F21V21/00

CPC分类号： B29C45/0025 ,  H01L33/483 ,  Y10S362/80

摘要： A forming mold of a light-emitting member includes a frame, an upper mold and a lower mold, and the frame is provided with carriers, pins and supporting portions. The upper and lower molds match with each other to provide a forming space for the base of the light-emitting member. The forming space contains the carriers and a part of the supporting portions. One or more projections are disposed at the position where the brinks of the upper and lower molds contact the supporting portions. After injection molding, the burrs formed by a plastic material along the supporting portions can be concealed in the recesses that are formed corresponding to each of the projections, thereby reducing the influence of the burrs on the external size of the base.

摘要翻译： 发光构件的成形模具包括框架，上模具和下模具，并且框架设置有托架，销和支撑部分。 上模具和下模具彼此匹配以提供用于发光构件的基部的成形空间。 成形空间包含载体和支撑部分的一部分。 一个或多个突起设置在上模具和下模具的边缘接触支撑部分的位置处。 在注射成型之后，沿着支撑部分由塑料材料形成的毛刺可以隐藏在对应于每个突起形成的凹部中，从而减少毛刺对基部的外部尺寸的影响。

公开(公告)号：US20120012886A1

公开(公告)日：2012-01-19

申请号：US13184316

申请日：2011-07-15

申请人： Chang-Han Chen ,  Chin-Chang Hsu

发明人： Chang-Han Chen ,  Chin-Chang Hsu

IPC分类号： H01L33/62 ,  B21D33/00 ,  F21V21/00

CPC分类号： H01L33/62 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/642 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2933/0066 ,  H01L2933/0075 ,  H01L2924/00014

摘要： A single material tape is shaped into first, second and third frames isolated from and disposed opposite each other, and a press forming process is performed to thin bottoms of first and second wire-bonding sectors extending from the first and second frames. The thickness of each of the first and second wire-bonding sectors is smaller than that of the third frame, so that the thicker third frame can be exposed out of a glue body to achieve the better dissipation effect, and at least one side surface between the two frames isolated from and disposed opposite each other is formed with a slot portion. When the frame is applied to the light emitting diode and fixed to the glue body, the slot portion can increase the bonding property between the frame and the glue body, and the structural strength therebetween can be increased.

摘要翻译： 单个材料带被成形为从彼此隔离并相对设置的第一，第二和第三框架，并且执行冲压成形过程以从第一和第二框架延伸的第一和第二引线键合扇区的薄底部。 第一和第二引线接合扇区中的每一个的厚度小于第三框架的厚度，使得较厚的第三框架可以从胶体露出以实现更好的散热效果，并且至少一个侧面 由彼此隔离并彼此相对设置的两个框架形成有狭槽部分。 当将框架施加到发光二极管并固定到胶体时，槽部分可以增加框架和胶体之间的结合性能，并且可以增加它们之间的结构强度。

公开(公告)号：USD635529S1

公开(公告)日：2011-04-05

申请号：US29366454

申请日：2010-07-26

申请人： Chin-Chang Hsu

设计人： Chin-Chang Hsu