公开(公告)号：US09667095B2

公开(公告)日：2017-05-30

申请号：US14182288

申请日：2014-02-18

Applicant: Shu-Hao Li ,  Kuo-Chan Huang ,  Yi-Hsun Lin ,  Tzu-Chiang Mi

Inventor： Shu-Hao Li ,  Kuo-Chan Huang ,  Yi-Hsun Lin ,  Tzu-Chiang Mi

IPC: H01H47/00 ,  H02J9/00 ,  G06F1/32

CPC classification number: H02J9/005 ,  G06F1/3206 ,  G06F1/3234 ,  Y10T307/826

Abstract: An electronic apparatus is provided. The electronic apparatus includes a controller, a first trigger circuit, a switch unit and a logic circuit. The controller provides a setting signal. The first trigger circuit provides a trigger signal according to at least one of first trigger situations. The switch unit is connected to a power input terminal. The logic circuit adjusts a switching signal according to the setting signal and the trigger signal. The switch unit decides whether to provide an input voltage at the power input terminal to the electronic apparatus according to the switching signal.

公开(公告)号：US07986171B2

公开(公告)日：2011-07-26

申请号：US12289132

申请日：2008-10-21

Applicant: Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

Inventor： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

IPC: H03B1/00

CPC classification number: H03K19/0013 ,  H03K3/356113 ,  H03K19/018521

Abstract: A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current.

Abstract translation: 混合电压输入/输出（I / O）缓冲器包括输出缓冲电路。 输出缓冲电路包括输出级电路，栅极跟踪电路和浮动N阱电路。 输出级电路包括堆叠上拉P型晶体管和堆叠式下拉式N型晶体管，其中堆叠上拉P型晶体管的第一P型晶体管和第一N型晶体管 堆叠的下拉式N型晶体管耦合到I / O焊盘。 栅极跟踪电路根据I / O焊盘的电压来控制第一P型晶体管的栅极电压，以防止漏电流。 浮动N阱电路为第一P型晶体管的N阱和第二P型晶体管的N阱提供N阱电压，控制栅极的第一P型晶体管的栅极电压 跟踪电路，以防止漏电流。

公开(公告)号：US20090108870A1

公开(公告)日：2009-04-30

申请号：US12193299

申请日：2008-08-18

Applicant: Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

Inventor： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

IPC: H03K19/0185 ,  H03L5/00

CPC classification number: H03K19/018521 ,  H03K19/018528

Abstract: An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.

Abstract translation: 提供输出缓冲电路。 输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。 输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。 电源电压被调整为上拉或下拉输出信号的第一电压电平。

公开(公告)号：US07501862B2

公开(公告)日：2009-03-10

申请号：US11767283

申请日：2007-06-22

Applicant: Tsung-Yi Su ,  Kuo-Chan Huang

Inventor： Tsung-Yi Su ,  Kuo-Chan Huang

IPC: H03K5/22

CPC classification number: H03K3/356113 ,  H03K3/356121

Abstract: A differential comparator is provided. The comparator receiving two differential signals and generating a comparison result represented by an output signal on one of two output terminals respectively on two current paths. The comparator comprises two pairs of latch transistors respectively disposed on the two current paths and two pairs of input transistors respectively disposed on the two current paths, wherein gates of the latch transistors on one of the current paths are commonly coupled to the output terminal between the latch transistors on the other current path, gates of the input transistors on one of the current paths respectively receives an input signal of one of the differential signals and a reference signal of the other differential signal and each of the input transistors is disposed between the output terminal and one of the latch transistors on the current path thereof.

Abstract translation: 提供差分比较器。 比较器接收两个差分信号，并且分别在两个电流路径上的两个输出端子之一上产生由输出信号表示的比较结果。 比较器包括分别设置在两个电流路径上的两对锁存晶体管和分别设置在两个电流路径上的两对输入晶体管，其中一条电​​流路径上的锁存晶体管的栅极共同耦合到输出端之间 在另一电流路径上的锁存晶体管，其中一条电​​流路径上的输入晶体管的栅极分别接收差分信号之一的输入信号和另一个差分信号的参考信号，并且每个输入晶体管设置在输出 端子和其电流路径上的锁存晶体管中的一个。

公开(公告)号：US20080151135A1

公开(公告)日：2008-06-26

申请号：US11905564

申请日：2007-10-02

Applicant: Hung-Ming Yang ,  Kuo-Chan Huang ,  Lin-Kai Bu

Inventor： Hung-Ming Yang ,  Kuo-Chan Huang ,  Lin-Kai Bu

IPC: G02F1/133 ,  G11C17/00

CPC classification number: G11C17/18 ,  G09G3/3655 ,  G09G2320/0693

Abstract: A common voltage adjustment apparatus for adjusting a common voltage of a liquid crystal display (LCD) panel includes a data-read-write circuit and an output circuit. The data-read-write circuit includes a one-time-programmable (OTP) memory module and a control interface unit. The OTP memory module includes several OTP memories. The control interface unit outputs common-voltage-setting data according to a control signal and selectively stores the common-voltage-setting data into an unwritten OTP memory in the OTP memory module. The output circuit includes a reference-voltage generator and a digital-to-analog converter (DAC). The reference-voltage generator generates a reference voltage. The DAC converts the common-voltage-setting data into an output voltage according to the reference voltage.

Abstract translation: 用于调节液晶显示​​器（LCD）面板的公共电压的公共电压调节装置包括数据读写电路和输出电路。 数据读写电路包括一次可编程（OTP）存储器模块和控制接口单元。 OTP存储器模块包括几个OTP存储器。 控制接口单元根据控制信号输出公共电压设定数据，并选择性地将公共电压设定数据存储在OTP存储器模块中的未写入的OTP存储器中。 输出电路包括参考电压发生器和数模转换器（DAC）。 参考电压发生器产生参考电压。 DAC根据参考电压将公共电压设置数据转换为输出电压。

公开(公告)号：US20180333003A1

公开(公告)日：2018-11-22

申请号：US15299082

申请日：2016-10-20

Applicant: Kuo-Chan Huang

Inventor： Kuo-Chan Huang

IPC: A47J37/07

CPC classification number: A47J37/079 ,  A47J2037/0777

Abstract: A stoking apparatus includes two concealable panels, a bent covering panel and a flat covering panel. The concealable panels are pivotally connected to each other. The bent covering panel includes a major portion and a minor portion, with an angle between the major and minor portions. The major portion is pivotally connected to one of the concealable panels. The minor portion is pivotally connected to the flat covering panel. The flat covering panel is further pivotally connected to the other concealable panel. The minor portion provides a gap between the major portion and the flat covering panel to receive the first and second concealable panels when the collapsible stoking apparatus is in a collapsed position.

公开(公告)号：US20140232205A1

公开(公告)日：2014-08-21

申请号：US14182288

申请日：2014-02-18

Applicant: Shu-Hao Li ,  Kuo-Chan Huang ,  Yi-Hsun Lin ,  Tzu-Chiang Mi

Inventor： Shu-Hao Li ,  Kuo-Chan Huang ,  Yi-Hsun Lin ,  Tzu-Chiang Mi

IPC: H02J9/00

CPC classification number: H02J9/005 ,  G06F1/3206 ,  G06F1/3234 ,  Y10T307/826

Abstract: An electronic apparatus is provided. The electronic apparatus includes a controller, a first trigger circuit, a switch unit and a logic circuit. The controller provides a setting signal. The first trigger circuit provides a trigger signal according to at least one of first trigger situations. The switch unit is connected to a power input terminal. The logic circuit adjusts a switching signal according to the setting signal and the trigger signal. The switch unit decides whether to provide an input voltage at the power input terminal to the electronic apparatus according to the switching signal.

Abstract translation: 提供电子设备。 电子设备包括控制器，第一触发电路，开关单元和逻辑电路。 控制器提供设置信号。 第一触发电路根据第一触发情况中的至少一个提供触发信号。 开关单元连接到电源输入端子。 逻辑电路根据设定信号和触发信号调整切换信号。 开关单元根据切换信号决定是否在电力输入端子向电子设备提供输入电压。

公开(公告)号：US20110241752A1

公开(公告)日：2011-10-06

申请号：US13067598

申请日：2011-06-13

Applicant: Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

Inventor： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

IPC: H03K5/08

CPC classification number: H03K19/0013 ,  H03K3/356113 ,  H03K19/018521

Abstract: A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.

Abstract translation: 混合电压I / O缓冲器包括输入缓冲电路。 输入缓冲电路包括第一反相器，第一电压电平限制电路，第一电压电平上拉电路，输入级电路和逻辑校准电路。 第一反相器反相输入信号以产生第一控制信号。 第一电压电平限制电路限制外部信号的电压电平，以产生传输到第一逆变器的输入信号，以防止第一逆变器的电过载。 第一电压上拉电路由第一控制信号控制，以提高输入到第一反相器的输入信号的电压电平。 输入级电路接收第一控制信号以产生输入到核心电路的相应的数字信号。 当由于输入信号具有低电压电平而使第一反相器误操作时，逻辑校准电路校准第一控制信号的电压电平。

公开(公告)号：US07957923B2

公开(公告)日：2011-06-07

申请号：US12117176

申请日：2008-05-08

Applicant: An-Sheng Chao ,  Soon-Jyh Chang ,  Chih-Haur Huang ,  Kuo-Chan Huang ,  Shih-Ming Luo

Inventor： An-Sheng Chao ,  Soon-Jyh Chang ,  Chih-Haur Huang ,  Kuo-Chan Huang ,  Shih-Ming Luo

IPC: G06F19/00 ,  H04B3/46

CPC classification number: G01R31/31709

Abstract: The device for jitter measurement and a method thereof are provided. The device for jitter measure includes a signal retrieving module, a signal amplifying module, an edge detecting module, and a time-to-digital converting module. The signal retrieving module receives a signal-under-test, and retrieves a first pulse signal having a pulse width equal to a period of the signal-under-test. The signal amplifying module amplifies the pulse width of the first pulse signal and thereby generates a second pulse signal. The edge detecting module detects a rising edge and a falling edge of the second pulse signal, and generates a first indication signal and a second indication signal according to the respective detected results. The time-to-digital converting module converts the pulse width of the second pulse signal existed in time domain to a digital signal according to the first indication signal and the second indication signal.

Abstract translation: 提供抖动测量装置及其方法。 用于抖动测量的装置包括信号检索模块，信号放大模块，边缘检测模块和时间 - 数字转换模块。 信号检索模块接收待测信号，并检索具有等于被测信号的周期的脉冲宽度的第一脉冲信号。 信号放大模块放大第一脉冲信号的脉冲宽度，从而产生第二脉冲信号。 边缘检测模块检测第二脉冲信号的上升沿和下降沿，并根据各个检测结果生成第一指示信号和第二指示信号。 时间 - 数字转换模块根据第一指示信号和第二指示信号将时域中存在的第二脉冲信号的脉冲宽度转换为数字信号。

公开(公告)号：US07839174B2

公开(公告)日：2010-11-23

申请号：US12330768

申请日：2008-12-09

Applicant: Chua-Chin Wang ,  Tzung-Je Lee ,  Yi-Cheng Liu ,  Kuo-Chan Huang

Inventor： Chua-Chin Wang ,  Tzung-Je Lee ,  Yi-Cheng Liu ,  Kuo-Chan Huang

IPC: H03K19/094

CPC classification number: H03K19/018521

Abstract: An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.

Abstract translation: 输出缓冲电路包括高电压检测电路，动态栅极偏置产生电路，输出级电路和焊盘电压检测器。 高电压检测电路检测电源电压，并根据电源电压产生第一和第二确定信号以及第一和第二偏置电压。 动态栅极偏置产生电路被第一和第二偏置电压偏置，并接收第一和第二确定信号，用于根据第一和第二确定信号将逻辑控制信号转换成相应的栅极偏置电压。 焊盘电压检测器检测I / O焊盘的电压，并为输出级电路提供焊盘电压检测信号，以修改输出到I / O焊盘的输出信号。 本文公开了混合电压输入/输出（I / O）缓冲器。