公开(公告)号：US07957923B2

公开(公告)日：2011-06-07

申请号：US12117176

申请日：2008-05-08

申请人： An-Sheng Chao ,  Soon-Jyh Chang ,  Chih-Haur Huang ,  Kuo-Chan Huang ,  Shih-Ming Luo

发明人： An-Sheng Chao ,  Soon-Jyh Chang ,  Chih-Haur Huang ,  Kuo-Chan Huang ,  Shih-Ming Luo

IPC分类号： G06F19/00 ,  H04B3/46

CPC分类号： G01R31/31709

摘要： The device for jitter measurement and a method thereof are provided. The device for jitter measure includes a signal retrieving module, a signal amplifying module, an edge detecting module, and a time-to-digital converting module. The signal retrieving module receives a signal-under-test, and retrieves a first pulse signal having a pulse width equal to a period of the signal-under-test. The signal amplifying module amplifies the pulse width of the first pulse signal and thereby generates a second pulse signal. The edge detecting module detects a rising edge and a falling edge of the second pulse signal, and generates a first indication signal and a second indication signal according to the respective detected results. The time-to-digital converting module converts the pulse width of the second pulse signal existed in time domain to a digital signal according to the first indication signal and the second indication signal.

摘要翻译： 提供抖动测量装置及其方法。 用于抖动测量的装置包括信号检索模块，信号放大模块，边缘检测模块和时间 - 数字转换模块。 信号检索模块接收待测信号，并检索具有等于被测信号的周期的脉冲宽度的第一脉冲信号。 信号放大模块放大第一脉冲信号的脉冲宽度，从而产生第二脉冲信号。 边缘检测模块检测第二脉冲信号的上升沿和下降沿，并根据各个检测结果生成第一指示信号和第二指示信号。 时间 - 数字转换模块根据第一指示信号和第二指示信号将时域中存在的第二脉冲信号的脉冲宽度转换为数字信号。

公开(公告)号：US20090112499A1

公开(公告)日：2009-04-30

申请号：US12117176

申请日：2008-05-08

申请人： An-Sheng Chao ,  Soon-Jyh Chang ,  Chih-Haur Huang ,  Kuo-Chan Huang ,  Shih-Ming Luo

发明人： An-Sheng Chao ,  Soon-Jyh Chang ,  Chih-Haur Huang ,  Kuo-Chan Huang ,  Shih-Ming Luo

IPC分类号： G01R29/26

CPC分类号： G01R31/31709

摘要： The device for jitter measurement and a method thereof are provided. The device for jitter measure includes a signal retrieving module, a signal amplifying module, an edge detecting module, and a time-to-digital converting module. The signal retrieving module receives a signal-under-test, and retrieves a first pulse signal having a pulse width equal to a period of the signal-under-test. The signal amplifying module amplifies the pulse width of the first pulse signal and thereby generates a second pulse signal. The edge detecting module detects a rising edge and a falling edge of the second pulse signal, and generates a first indication signal and a second indication signal according to the respective detected results. The time-to-digital converting module converts the pulse width of the second pulse signal existed in time domain to a digital signal according to the first indication signal and the second indication signal.

摘要翻译： 提供抖动测量装置及其方法。 用于抖动测量的装置包括信号检索模块，信号放大模块，边缘检测模块和时间 - 数字转换模块。 信号检索模块接收待测信号，并检索具有等于被测信号的周期的脉冲宽度的第一脉冲信号。 信号放大模块放大第一脉冲信号的脉冲宽度，从而产生第二脉冲信号。 边缘检测模块检测第二脉冲信号的上升沿和下降沿，并根据各个检测结果生成第一指示信号和第二指示信号。 时间 - 数字转换模块根据第一指示信号和第二指示信号将时域中存在的第二脉冲信号的脉冲宽度转换为数字信号。

公开(公告)号：US07924204B2

公开(公告)日：2011-04-12

申请号：US12247186

申请日：2008-10-07

申请人： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

发明人： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC分类号： H03M1/38

CPC分类号： H03M1/1225 ,  H03M1/0695 ,  H03M1/162 ,  H03M1/164 ,  H03M1/40 ,  H03M1/44

摘要： An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.

摘要翻译： 公开了一种用于流水线ADC或循环ADC的模数转换器（ADC）。 ADC包括串联连接的至少一对两个级，两级具有不同的分辨率。 放大器由一对两个级共享，使得两个级以交错方式操作。 因此，这种阶段分辨率可扩展的运算放大器共享技术适用于流水线ADC或循环ADC，这大大降低了功耗并提高了运行速度。

公开(公告)号：US20100134173A1

公开(公告)日：2010-06-03

申请号：US12326854

申请日：2008-12-02

申请人： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

发明人： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC分类号： G06G7/184

CPC分类号： H03F3/005 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45654 ,  H03F2200/78 ,  H03F2203/45136 ,  H03F2203/45404 ,  H03F2203/45648

摘要： A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout−) at a desirable level.

摘要翻译： 公开了一种使用基于积分器的共模稳定技术的伪差分开关电容器电路。 具有差分浮动采样（DFS）技术的伪差分开关电容电路具有1（1）的共模增益值。 积分器电耦合到DFS电路的差分正/负输出，积分器通过检测差分正输出（Vout +）和负输出（Vout-）的共模电压干扰，将积分器输出反馈到DFS电路。 从而将差分正输出（Vout +）和负输出（Vout-）的输出共模电平稳定在理想水平。

公开(公告)号：US07724174B2

公开(公告)日：2010-05-25

申请号：US12247199

申请日：2008-10-07

申请人： Soon-Jyh Chang ,  Chun-Cheng Liu ,  Chih-Haur Huang

发明人： Soon-Jyh Chang ,  Chun-Cheng Liu ,  Chih-Haur Huang

IPC分类号： H03M1/34

CPC分类号： H03M1/069 ,  H03M1/466 ,  H03M1/804

摘要： A successive approximation ADC is disclosed. A comparator receives and compares a sampled input signal and an output of a DAC. Non-binary successive approximation register (SAR) control logic controls sampling of the input signal and controls a sequence of comparisons based on comparison result of the comparator. The SAR control logic controls each comparison when signal or charge in the DAC has not been completely settled. A binary-error-tolerant corrector is then used to compensate the sampling error.

摘要翻译： 公开了逐次逼近ADC。 比较器接收并比较采样的输入信号和DAC的输出。 非二进制逐次逼近寄存器（SAR）控制逻辑控制输入信号的采样，并根据比较器的比较结果控制比较序列。 当DAC中的信号或电荷未完全稳定时，SAR控制逻辑控制每个比较。 然后使用二进制容错校正器来补偿采样误差。

公开(公告)号：US20100085227A1

公开(公告)日：2010-04-08

申请号：US12247186

申请日：2008-10-07

申请人： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

发明人： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC分类号： H03M1/10

CPC分类号： H03M1/1225 ,  H03M1/0695 ,  H03M1/162 ,  H03M1/164 ,  H03M1/40 ,  H03M1/44

摘要： An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.

摘要翻译： 公开了一种用于流水线ADC或循环ADC的模数转换器（ADC）。 ADC包括串联连接的至少一对两级，两级具有不同的分辨率。 放大器由一对两个级共享，使得两个级以交错方式操作。 因此，这种阶段分辨率可扩展的运算放大器共享技术适用于流水线ADC或循环ADC，这大大降低了功耗并提高了运行速度。

公开(公告)号：US08390501B2

公开(公告)日：2013-03-05

申请号：US13096908

申请日：2011-04-28

申请人： Soon-Jyh Chang ,  Guan-Ying Huang ,  Chun-Cheng Liu ,  Chung-Ming Huang ,  Jin-Fu Lin ,  Chih-Haur Huang

发明人： Soon-Jyh Chang ,  Guan-Ying Huang ,  Chun-Cheng Liu ,  Chung-Ming Huang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC分类号： H03M1/34

CPC分类号： H03M1/462 ,  H03M1/466

摘要： A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.

摘要翻译： 公开了逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 第一和第二电容器DAC分别接收第一和第二输入信号。 第一粗略比较器将第一电容器DAC的输出与窗口参考电压进行比较，第二粗略比较器将第二电容器DAC的输出与窗口参考电压进行比较，精细比较器将第一电容器DAC的输出与 第二电容DAC的输出。 SAR控制器接收第一和第二粗略比较器的输出，以确定第一和第二电容器DAC的输出是否在由窗口参考电压确定的预测窗口内。 当第一电容器DAC和第二电容器DAC的输出被确定为在预测窗口内时，SAR控制器绕过至少一个SAR模数转换阶段。 SAR控制器解码第一和第二粗略比较器和精细比较器的输出，以获得SAR ADC的转换输出。

公开(公告)号：US20100085225A1

公开(公告)日：2010-04-08

申请号：US12247199

申请日：2008-10-07

申请人： Soon-Jyh Chang ,  Chun-Cheng Liu ,  Chih-Haur Huang

发明人： Soon-Jyh Chang ,  Chun-Cheng Liu ,  Chih-Haur Huang

IPC分类号： H03M1/00 ,  H03M1/38 ,  H03M1/06

CPC分类号： H03M1/069 ,  H03M1/466 ,  H03M1/804

摘要： A successive approximation ADC is disclosed. A comparator receives and compares a sampled input signal and an output of a DAC. Non-binary successive approximation register (SAR) control logic controls sampling of the input signal and controls a sequence of comparisons based on comparison result of the comparator. The SAR control logic controls each comparison when signal or charge in the DAC has not been completely settled. A binary-error-tolerant corrector is then used to compensate the sampling error.

摘要翻译： 公开了逐次逼近ADC。 比较器接收并比较采样的输入信号和DAC的输出。 非二进制逐次逼近寄存器（SAR）控制逻辑控制输入信号的采样，并根据比较器的比较结果控制比较序列。 当DAC中的信号或电荷未完全稳定时，SAR控制逻辑控制每个比较。 然后使用二进制容错校正器来补偿采样误差。

公开(公告)号：US07724063B1

公开(公告)日：2010-05-25

申请号：US12326854

申请日：2008-12-02

申请人： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

发明人： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC分类号： H03F1/02

CPC分类号： H03F3/005 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45654 ,  H03F2200/78 ,  H03F2203/45136 ,  H03F2203/45404 ,  H03F2203/45648

摘要： A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout−) at a desirable level.

摘要翻译： 公开了一种使用基于积分器的共模稳定技术的伪差分开关电容器电路。 具有差分浮动采样（DFS）技术的伪差分开关电容电路具有1（1）的共模增益值。 积分器电耦合到DFS电路的差分正/负输出，积分器通过检测差分正输出（Vout +）和负输出（Vout-）的共模电压干扰，将积分器输出反馈到DFS电路。 从而将差分正输出（Vout +）和负输出（Vout-）的输出共模电平稳定在理想水平。

公开(公告)号：US07602324B1

公开(公告)日：2009-10-13

申请号：US12356107

申请日：2009-01-20

申请人： Chih-Haur Huang ,  Kuo-Chan Huang

发明人： Chih-Haur Huang ,  Kuo-Chan Huang

IPC分类号： H03M1/20

CPC分类号： H03M1/0641 ,  H03M1/0695 ,  H03M1/164 ,  H03M1/44

摘要： A method for converting analog signals into digital signals includes the steps of: superimposing a dither value on an analog input signal; sampling the superimposition of the analog input signal with the dither value to obtain a sampling signal; converting the sampling signal into corresponding digital values; correcting offsets in the digital values to generate a digital signal; and removing the dither value from the digital signal. An analog-to-digital converter is also disclosed herein.

摘要翻译： 一种将模拟信号转换为数字信号的方法包括以下步骤：将抖动值叠加在模拟输入信号上; 对模拟输入信号与抖动值的叠加进行取样以获得采样信号; 将采样信号转换成相应的数字值; 校正数字值中的偏移量以产生数字信号; 并从数字信号中去除抖动值。 本文还公开了一种模拟 - 数字转换器。