公开(公告)号：US10305670B2

公开(公告)日：2019-05-28

申请号：US16021793

申请日：2018-06-28

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart

IPC: H04L5/16 ,  H04L7/00

Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.

公开(公告)号：US09875197B2

公开(公告)日：2018-01-23

申请号：US15063902

申请日：2016-03-08

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart

IPC: G06F13/22 ,  G06F13/42 ,  H04L12/403 ,  G06F11/10 ,  G06F13/16 ,  H03M13/09

CPC classification number: G06F13/22 ,  G06F11/1004 ,  G06F13/1642 ,  G06F13/4282 ,  H03M13/09 ,  H04L12/403

Abstract: A method is provided for use in a host module, for identifying at least one accessory module on a bus, wherein the bus is configured to allow multiple accessory modules to be connected to the host module. The method includes sending a query to any accessory module connected to the bus, the query concerning whether the or each accessory module meets a specified criterion; and receiving synchronized responses from any accessory module that meets the specified criterion connected to the bus where said responses are specific to the query but non-specific to an effectively uniquely distinguishing feature of the individual module. It is then possible to determine from redundant information contained in an aggregate of the synchronized responses whether there is (a) no accessory module meeting the specified criterion, or (b) at least one accessory module meeting the specified criterion.

公开(公告)号：US20160344536A1

公开(公告)日：2016-11-24

申请号：US15159760

申请日：2016-05-19

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Bhoodev Kumar ,  Muraleedharan Ramakrishnan ,  Vivek Oppula ,  Thomas Hoff ,  Willem Zwart

IPC: H04L7/00

CPC classification number: H04L7/0008 ,  G06F13/40 ,  G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

Abstract: Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.

Abstract translation: 可以通过主设备和从设备之间的有线连接在通信路径上执行同步差分信令，以提供高带宽和/或低延迟通信。 可以通过提供可配置的帧结构在信令协议中提供灵活性。 灵活性可以在数据流映射到帧中的位时隙，改变下行链路和上行链路时隙数量，配置多个周转时间以及帧内周转的位置，配置控制字位（CWB）的位置和数量的情况下， 时隙，和/或调整通信链路的时钟频率。

公开(公告)号：US20160269201A1

公开(公告)日：2016-09-15

申请号：US14928766

申请日：2015-10-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart ,  Bhupendra Singh Manola

IPC: H04L25/02 ,  H04L5/14 ,  H04L5/16

CPC classification number: H04L25/0276 ,  H04B3/30 ,  H04L5/1461 ,  H04L5/16

Abstract: A system comprises a first module and a second module, connected by a transmission line comprising first and second wires. The first module includes common mode voltage circuitry, for imposing a common mode voltage onto the first and second wires. The first module includes signal generation circuitry, for generating a signal voltage in response to first data, and for imposing the signal voltage as a differential signal onto the first and second wires during periods when the first module has first data to transmit. The second module includes current generation circuitry, for generating a signal current in response to second data, and for injecting the signal current as a differential current onto the first and second wires during periods when the second module has second data to transmit. The first module includes respective resistances connected to the first and second wires. The first module includes a first detector for obtaining first output data based on voltages across the resistors resulting from the signal current injected by the current generation circuitry of the second module; and the second module includes a second detector for obtaining second output data based on differential signal imposed by the signal generation circuitry of the first module.

Abstract translation: 一种系统包括第一模块和第二模块，通过包括第一和第二导线的传输线连接。 第一模块包括共模电压电路，用于在第一和第二导线上施加共模电压。 第一模块包括用于响应于第一数据产生信号电压的信号产生电路，并且用于在第一模块具有第一数据要发送的时段期间将信号电压作为差分信号施加到第一和第二导线上。 第二模块包括用于响应于第二数据产生信号电流的当前产生电路，以及用于在第二模块具有第二数据传输的期间将作为差分电流的信号电流注入到第一和第二导线上。 第一模块包括连接到第一和第二导线的各自的电阻。 第一模块包括第一检测器，用于基于由第二模块的当前产生电路注入的信号电流产生的电阻，获得第一输出数据; 并且第二模块包括第二检测器，用于基于由第一模块的信号产生电路施加的差分信号获得第二输出数据。