公开(公告)号：US20100020587A1

公开(公告)日：2010-01-28

申请号：US12505820

申请日：2009-07-20

申请人： Sumiko DOUMAE ,  Daisaburo Takashima

发明人： Sumiko DOUMAE ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  G11C7/06 ,  G11C5/14 ,  G11C5/06

CPC分类号： G11C11/22 ,  G11C5/147 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/5002

摘要： A ferroelectric memory is provided with a voltage generating circuit configured to generate prescribed driving potential, a driving interconnection to which the driving potential is applied, a plurality of memory cells connected to the driving interconnections and an internal voltage comparison circuit configured to compare inputted potential and to output results thereof. A plurality of voltage monitoring interconnections are provided to connect between a portion of the driving interconnection disposed at a position distant from the voltage generating circuit on the substrate and the internal voltage comparison circuit. The internal voltage comparison circuit compares potential inputted through the voltage monitoring interconnection with the driving potential.

摘要翻译： 铁电存储器设置有电压产生电路，其被配置为产生规定的驱动电位，施加驱动电位的驱动互连，连接到驱动互连的多个存储单元，以及内部电压比较电路，被配置为将输入的电位和 输出结果。 提供多个电压监视互连以连接布置在远离衬底上的电压产生电路的位置处的驱动互连部分和内部电压比较电路之间。 内部电压比较电路将通过电压监视互连输入的电位与驱动电位进行比较。

公开(公告)号：US20100011260A1

公开(公告)日：2010-01-14

申请号：US12513860

申请日：2007-11-28

申请人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda ,  Shinichi Kanno

发明人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda ,  Shinichi Kanno

IPC分类号： G11C29/04 ,  G06F11/22 ,  G06F11/00

CPC分类号： G11C16/349 ,  G06F11/008 ,  G06F11/1068

摘要： To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.

摘要翻译： 提供一种确定诸如耗尽水平的存储器状态并且允许有效地使用存储器的存储器系统。 存储器系统包括NAND型闪速存储器1，数据可以被电写入/擦除;非易失性存储器2，对NAND型闪速存储器1的擦除操作次数进行计数，并保持擦除次数和最大数量 擦除操作，以及控制器3，其具有从计算机4被给予自诊断命令的连接接口31，并且基于自身检测从非易失性存储器2检索擦除操作的次数和擦除操作的最大次数， 诊断命令，并通过连接接口31输出擦除操作次数和最大擦除次数。

公开(公告)号：US07589513B2

公开(公告)日：2009-09-15

申请号：US11783039

申请日：2007-04-05

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G05F3/16

CPC分类号： G05F3/30 ,  G11C5/147 ,  G11C7/04

摘要： A reference voltage generator circuit comprises a first current path and a second current path. The first current path is formed between an input terminal supplied with a first reference voltage and an output terminal and including a first diode and a first resistor serially connected from the input terminal. The second current path is formed between the input terminal and the output terminal and including a second diode, a second resistor and a third resistor serially connected from the input terminal. A comparator is supplied with a voltage on a node between the first diode and the first resistor and a voltage on a node between the second resistor and the third resistor for comparative amplification. A transistor is connected between the output terminal and a second reference voltage and having a control terminal to receive an output from the first comparator.

摘要翻译： 参考电压发生器电路包括第一电流路径和第二电流路径。 第一电流路径形成在提供有第一参考电压的输入端子和输出端子之间，并且包括第一二极管和从输入端子串联连接的第一电阻器。 第二电流路径形成在输入端子和输出端子之间，并且包括从输入端子串联连接的第二二极管，第二电阻器和第三电阻器。 比较器在第一二极管和第一电阻之间的节点上提供电压，并且在第二电阻器和第三电阻器之间的节点上的电压用于比较放大。 晶体管连接在输出端和第二参考电压之间，并且具有用于接收来自第一比较器的输出的控制端。

公开(公告)号：US07583114B2

公开(公告)日：2009-09-01

申请号：US11684214

申请日：2007-03-09

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： H03L7/00

CPC分类号： G01R19/16552 ,  G01R19/16519 ,  G11C5/147

摘要： A supply voltage sensing circuit comprises an internal power supply circuit, which provides a constant output voltage regardless of the supply voltage. A delay circuit generates a delayed signal by delaying a variation in the output voltage. A divider circuit generates a divided voltage by dividing the supply voltage at a certain division ratio. A p-type MOS transistor has a source given the delayed signal and a gate given the divided voltage and turns on when the supply voltage lowers below a certain value. An output circuit provides an output voltage based on a drain voltage on the p-type MOS transistor.

摘要翻译： 电源电压检测电路包括内部电源电路，其提供恒定的输出电压，而不管电源电压如何。 延迟电路通过延迟输出电压的变化来产生延迟信号。 分压电路通过以一定的分频比除电源电压来产生分压。 p型MOS晶体管具有给定延迟信号的源极和给定分压的栅极，并且当电源电压降低到一定值以下时导通。 输出电路基于p型MOS晶体管上的漏极电压提供输出电压。

公开(公告)号：US07443709B2

公开(公告)日：2008-10-28

申请号：US11599363

申请日：2006-11-15

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C29/02 ,  G11C5/147 ,  G11C7/04 ,  G11C7/062 ,  G11C7/14 ,  G11C11/22 ,  G11C29/026 ,  G11C29/028 ,  G11C2029/5002 ,  G11C2207/065

摘要： A first bit line is connected to a memory cell. A second bit line is connected to a dummy cell having a dummy capacitor, and supplied with an electric potential which is complementary to the electric potential of the first bit line. A sense amplifier compares and amplifies the first and second bit lines. A sense amplifier supply voltage generation circuit supplies the sense amplifier with a sense amplifier supply voltage to be used in the comparison and amplification by the sense amplifier. The sense amplifier supply voltage is supplied to a reference potential generation circuit. When data is read out from the memory cell to the first bit line, the reference potential generation circuit supplies, to the second bit line via the dummy cell, a reference potential which fluctuates with a positive correlation to the fluctuation in sense amplifier supply voltage.

摘要翻译： 第一位线连接到存储器单元。 第二位线连接到具有虚拟电容器的虚拟单元，并且提供与第一位线的电位互补的电位。 读出放大器比较和放大第一和第二位线。 读出放大器电源电压产生电路为读出放大器提供读出放大器电源电压，以便由读出放大器进行比较和放大。 读出放大器电源电压被提供给参考电位产生电路。 当数据从存储单元读出到第一位线时，参考电位产生电路经由虚拟单元向第二位线提供与读出放大器电源电压的波动成正相关的波动的基准电位。

公开(公告)号：US20080101107A1

公开(公告)日：2008-05-01

申请号：US11877890

申请日：2007-10-24

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  G11C7/00

CPC分类号： G11C11/22

摘要： A first ferroelectric memory cell and a second ferroelectric memory cell each include a ferroelectric capacitor and a transistor and each store one set of information. A word-line is shared by the first and second ferroelectric memory cells. A first plate line is connected to the first ferroelectric memory cell and a second plate line is connected to the second ferroelectric memory cell. A selection transistor has one end connected to the first and second ferroelectric memory cells and the other end connected to a bit-line.

摘要翻译： 第一铁电存储器单元和第二铁电存储单元各自包括铁电电容器和晶体管，并且每个存储一组信息。 字线由第一和第二铁电存储器单元共享。 第一板线连接到第一铁电存储单元，第二板线连接到第二铁电存储单元。 选择晶体管的一端连接到第一和第二铁电存储单元，另一端连接到位线。

公开(公告)号：US07298657B2

公开(公告)日：2007-11-20

申请号：US11347337

申请日：2006-02-06

申请人： Sumiko Domae ,  Daisaburo Takashima

发明人： Sumiko Domae ,  Daisaburo Takashima

IPC分类号： G11C29/00

CPC分类号： G11C11/22 ,  G11C29/816 ,  G11C29/84

摘要： A unit cell is composed of a memory cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the memory cell transistor. A memory cell block is composed of a plurality of unit cells connected in series. One end of the memory cell block is connected to a bit line via a block selecting transistor. The other end of the memory cell block is connected to a plate line. A redundancy unit cell is composed of a redundancy cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the redundancy cell transistor. A redundancy memory cell block is composed of a plurality of unit cells connected in series, the number of which is smaller than that of the unit cells in the memory cell block.

摘要翻译： 单元电池由在存储单元晶体管的源极和漏极之间并联连接的存储单元晶体管和铁电存储元件组成。 存储单元块由串联连接的多个单位单元构成。 存储单元块的一端通过块选择晶体管连接到位线。 存储单元块的另一端连接到板线。 冗余单元由冗余单元晶体管和并联在冗余单元晶体管的源极和漏极之间的铁电存储元件组成。 冗余存储器单元块由串联连接的多个单元单元组成，其数量小于存储单元块中单元单元的数量。

公开(公告)号：US07269049B2

公开(公告)日：2007-09-11

申请号：US11046878

申请日：2005-02-01

申请人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C7/14

摘要： A plurality of ferroelectric memory cells is arrayed. One terminal of each memory cells arrayed in the same column is connected in common to a first bit line. A gate of a transistor of memory cells arrayed in the same row is connected in common to a word line. The other terminal of each of memory cells arrayed in the same column or the same row is connected in common to a cell plate line. A second bit line is connected with a reference voltage supply circuit. The first and second bit lines are connected with a data read circuit. The data read circuit includes a sense amplifier and a current mirror circuit having a pair of current input node connected to the first and second bit lines, and carrying the same current flowing through one of the first and second bit line to the other bit line.

摘要翻译： 排列多个铁电存储单元。 排列在同一列中的每个存储单元的一个端子共同连接到第一位线。 排列在同一行中的存储单元的晶体管的栅极共同连接到字线。 排列在同一列或同一行中的每个存储单元的另一个端子共同连接到单元格板线。 第二位线与参考电压供应电路连接。 第一和第二位线与数据读取电路连接。 数据读取电路包括读出放大器和电流镜像电路，其具有连接到第一和第二位线的一对电流输入节点，并且将流过第一和第二位线之一的相同电流传送到另一位线。

公开(公告)号：US07257011B2

公开(公告)日：2007-08-14

申请号：US11258922

申请日：2005-10-27

申请人： Tadashi Miyakawa ,  Daisaburo Takashima

发明人： Tadashi Miyakawa ,  Daisaburo Takashima

IPC分类号： G11C5/08 ,  G11C5/06

CPC分类号： G11C11/22

摘要： A semiconductor memory according to an example of the present invention comprises first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns, a first cell block which is disposed in the first column, a first block select transistor which is connected between the first or second bit line and one end of the first cell block, a second cell block which is disposed in the second column, and a second block select transistor which is connected between the second or first bit line and one end of the second cell block.

摘要翻译： 根据本发明的示例的半导体存储器包括具有扭曲位线架构的第一和第二位线，其中第一和第二位线在第一和第二列中以恒定周期交替地扭曲;第一单元块，其 设置在第一列中，第一块选择晶体管连接在第一或第二位线与第一单元块的一端之间，第二单元块设置在第二列中，第二块选择晶体管， 连接在第二或第二位线与第二单元块的一端之间。

公开(公告)号：US07233536B2

公开(公告)日：2007-06-19

申请号：US11239219

申请日：2005-09-30

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G11C7/00

CPC分类号： G11C11/22

摘要： A semiconductor memory device includes a memory cell array, a sense amplifier, and a voltage generator. The memory cell array has a plurality of memory cells. Each of the memory cells is written with “0” or “1” as reference data after “0” or “1” as cell data has been read out from the memory cell. The sense amplifier compares and amplifies the reference data and the cell data read from a memory cell. The voltage generator keeps constant rate of change with time of at least one potential supplied for a read operation for the time interval from readout of the cell data is started until completion of readout of the reference data.

摘要翻译： 半导体存储器件包括存储单元阵列，读出放大器和电压发生器。 存储单元阵列具有多个存储单元。 在从存储单元读出单元数据的情况下，每个存储单元都以“0”或“1”作为参考数据写入“0”或“1”之后。 读出放大器比较和放大从存储器单元读取的参考数据和单元数据。 电压发生器在从开始单元数据的读出开始直至完成读出参考数据的时间间隔内，为读操作提供至少一个电位的时间保持恒定的变化率。