公开(公告)号：US07146482B2

公开(公告)日：2006-12-05

申请号：US10723506

申请日：2003-11-25

申请人： David F. Craddock ,  Richard K. Errickson ,  Mark S. Farrell ,  Charles W. Gainey, Jr. ,  Thomas A. Gregg ,  Carol B. Hernandez ,  Donald W. Schmidt

发明人： David F. Craddock ,  Richard K. Errickson ,  Mark S. Farrell ,  Charles W. Gainey, Jr. ,  Thomas A. Gregg ,  Carol B. Hernandez ,  Donald W. Schmidt

IPC分类号： G06F9/26

CPC分类号： G06F9/30003 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/342

摘要： A method of managing memory mapped input output operations to an alternate address space comprising: executing a first instruction directed to a first memory mapped input output alternate address space of a machine associated with a first adapter to allocate a resource associated with the first adapter to a process in accordance with a definition of a z/Architecture; wherein a selected process issues at least one of a load and a store instruction executed in a problem state of the machine to a selected address location of a selected resource. The method further includes ensuring that the selected resource corresponds with the allocated resource and determining that the selected process corresponds with the process to which the resource is allocated.

摘要翻译： 一种将存储器映射的输入输出操作管理到备用地址空间的方法，包括：执行指向与第一适配器相关联的机器的第一存储器映射输入输出备用地址空间的第一指令，以将与第一适配器相关联的资源分配给 过程按照az / Architecture的定义; 其中所选择的过程将所述机器的问题状态中执行的加载和存储指令中的至少一个发出到所选择的资源的所选地址位置。 该方法还包括确保所选择的资源对应于所分配的资源，并确定所选择的进程与分配资源的进程相对应。

公开(公告)号：US07552436B2

公开(公告)日：2009-06-23

申请号：US10723405

申请日：2003-11-25

申请人： Frank William Brice, Jr. ,  Richard K. Errickson ,  Mark S. Farrell ,  Charles W. Gainey, Jr. ,  Thomas A. Gregg ,  Carol B. Hernandez ,  Damian L. Osisek ,  Donald W. Schmidt

发明人： Frank William Brice, Jr. ,  Richard K. Errickson ,  Mark S. Farrell ,  Charles W. Gainey, Jr. ,  Thomas A. Gregg ,  Carol B. Hernandez ,  Damian L. Osisek ,  Donald W. Schmidt

IPC分类号： G06F9/46 ,  G06F3/00

CPC分类号： G06F12/0292 ,  G06F9/45537 ,  G06F2212/206

摘要： A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with a definition of a z/Architecture; allocating at least one of a real resource and a virtual resource associated with the first alternate address space to a process; ensuring that the selected process corresponds with the process to which the resource is allocated. The process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.

摘要翻译： 一种向备用地址空间执行存储器映射输入输出操作的方法，包括：根据z / Architecture的定义，建立指向与适配器相关联的第一存储器映射输入输出备用地址空间的第一指令以存储数据; 建立指向与适配器相关联的第一存储器映射输入输出交替地址空间的第二指令，以根据z / Architecture的定义加载数据; 将与所述第一替代地址空间相关联的实际资源和虚拟资源中的至少一个分配给进程; 确保所选择的进程与分配资源的进程相对应。 该过程发生第一指令和第二指令中的至少一个，从而导致使用第一替代地址空间执行存储和加载中的至少一个。

公开(公告)号：US08635430B2

公开(公告)日：2014-01-21

申请号：US12821170

申请日：2010-06-23

申请人： David Craddock ,  Thomas A. Gregg ,  Dan F. Greiner ,  Eric N. Lais

发明人： David Craddock ,  Thomas A. Gregg ,  Dan F. Greiner ,  Eric N. Lais

IPC分类号： G06F12/00

CPC分类号： G06F12/10 ,  G06F9/355 ,  G06F12/0292 ,  G06F2212/206

摘要： An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

公开(公告)号：US08468284B2

公开(公告)日：2013-06-18

申请号：US12821177

申请日：2010-06-23

申请人： Frank W. Brice, Jr. ,  David Craddock ,  Janet R. Easton ,  Mark S. Farrell ,  Thomas A. Gregg ,  Damian L. Osisek ,  Gustav E. Sittmann, III

发明人： Frank W. Brice, Jr. ,  David Craddock ,  Janet R. Easton ,  Mark S. Farrell ,  Thomas A. Gregg ,  Damian L. Osisek ,  Gustav E. Sittmann, III

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/541 ,  G06F9/545 ,  G06F13/24 ,  G06F2213/0026

摘要： One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used.

摘要翻译： 一个或多个来自一个或多个输入/输出（I / O）适配器的信号中断请求被转换为I / O适配器事件通知，同时保留消息向量指示。 可以将I / O适配器事件通知路由并呈现给主机或主机正在执行的guest虚拟机。 为了将通知呈现给正确的主机或正确的客户机，使用主机和/或来宾存储器中的各种数据结构。

公开(公告)号：US08458387B2

公开(公告)日：2013-06-04

申请号：US13446957

申请日：2012-04-13

申请人： Frank W. Brice, Jr. ,  David Craddock ,  Janet R. Easton ,  Mark S. Farrell ,  Thomas A. Gregg ,  Damian L. Osisek ,  Cynthia Sittmann

发明人： Frank W. Brice, Jr. ,  David Craddock ,  Janet R. Easton ,  Mark S. Farrell ,  Thomas A. Gregg ,  Damian L. Osisek ,  Gustav E. Sittmann, III

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/541 ,  G06F9/545 ,  G06F13/24 ,  G06F2213/0026

摘要： One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used.

公开(公告)号：US08265092B2

公开(公告)日：2012-09-11

申请号：US11855401

申请日：2007-09-14

申请人： David Craddock ,  Thomas A. Gregg ,  Thomas Schlipf

发明人： David Craddock ,  Thomas A. Gregg ,  Thomas Schlipf

IPC分类号： H04L12/28

CPC分类号： G06F13/4022

摘要： A receive queue provided in a computer system holds work completion information and message data together. An InfiniBand hardware adapter sends a single CQE+message data to the computer system that includes the completion Information and data. This information is sufficient for the computer system to receive and process the data message, thereby providing a highly scalable low latency receiving mechanism.

摘要翻译： 计算机系统中提供的接收队列将工作完成信息和消息数据保存在一起。 InfiniBand硬件适配器将单个CQE +消息数据发送到包括完成信息和数据的计算机系统。 该信息足以使计算机系统接收和处理数据消息，从而提供高度可扩展的低延迟接收机制。

公开(公告)号：US20110320757A1

公开(公告)日：2011-12-29

申请号：US12821194

申请日：2010-06-23

申请人： David Craddock ,  Mark S. Farrell ,  Thomas A. Gregg ,  Dan F. Greiner

发明人： David Craddock ,  Mark S. Farrell ,  Thomas A. Gregg ,  Dan F. Greiner

IPC分类号： G06F12/06

CPC分类号： G06F9/30043 ,  G06F9/3004

摘要： Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter.

摘要翻译： 与计算环境的适配器通信便利。 提供明确指定适配器的说明。 指令中提供的信息用于将指令转向适配器内的适当位置。

公开(公告)号：US20110320756A1

公开(公告)日：2011-12-29

申请号：US12821171

申请日：2010-06-23

申请人： David Craddock ,  Thomas A. Gregg ,  Dan F. Greiner ,  Eric N. Lais ,  Donald W. Schmidt

发明人： David Craddock ,  Thomas A. Gregg ,  Dan F. Greiner ,  Eric N. Lais ,  Donald W. Schmidt

IPC分类号： G06F12/10

CPC分类号： G06F13/28 ,  G06F12/1081

摘要： Various address translation formats are available for use in obtaining system memory addresses for use by requestors, such as adapter functions, in accessing system memory. The particular address translation format to be used by a given requestor is pre-registered in a device table entry associated with that requestor.

摘要翻译： 各种地址转换格式可用于获取系统内存地址以供请求者使用，如适配器功能，用于访问系统内存。 给定请求者使用的特定地址转换格式在与该请求者相关联的设备表条目中预先注册。

公开(公告)号：US20110320664A1

公开(公告)日：2011-12-29

申请号：US12821179

申请日：2010-06-23

申请人： Brenton F. Belmar ,  David Craddock ,  Janet R. Easton ,  Mark S. Farrell ,  Thomas A. Gregg ,  Damian L. Osisek ,  Donald W. Schmidt ,  Gustav E. Sittmann, III ,  Richard P. Tarcza

发明人： Brenton F. Belmar ,  David Craddock ,  Janet R. Easton ,  Mark S. Farrell ,  Thomas A. Gregg ,  Damian L. Osisek ,  Donald W. Schmidt ,  Gustav E. Sittmann, III ,  Richard P. Tarcza

IPC分类号： G06F13/24

CPC分类号： G06F9/4812

摘要： The conditions under which adapter interruptions are made pending are controlled. Responsive to an interruption being presented to an operating system, subsequent interruptions are suppressed on all central processing units in the configuration. The operating system processes the interruption, including examining and processing indicators of reported events until the operating system discontinues the suppression. This enables the operating system to control the number of pending interruptions and the number of processors processing those interruptions.

摘要翻译： 控制适配器中断的条件。 响应于向操作系统呈现的中断，在配置中的所有中央处理单元上抑制了后续中断。 操作系统处理中断，包括检查和处理报告事件的指示，直到操作系统停止抑制。 这使得操作系统能够控制待处理中断的次数和处理这些中断的处理器的数量。

公开(公告)号：US07895383B2

公开(公告)日：2011-02-22

申请号：US12043361

申请日：2008-03-06

申请人： Thomas A. Gregg ,  Richard L. Arndt ,  Bruce L. Beukema ,  David Craddock ,  Ronald E. Fuhs ,  Steven L. Rogers ,  Donald W. Schmidt ,  Bruce M. Walk

发明人： Thomas A. Gregg ,  Richard L. Arndt ,  Bruce L. Beukema ,  David Craddock ,  Ronald E. Fuhs ,  Steven L. Rogers ,  Donald W. Schmidt ,  Bruce M. Walk

IPC分类号： G06F13/24 ,  G06F3/00 ,  G06F13/40

CPC分类号： G06F9/546 ,  G06F2209/548 ,  H04L49/901

摘要： An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

摘要翻译： 提供了包括多个系统资源的信息处理系统和具有最大数量的条目的事件队列。 信息处理系统的事件记录机制可操作用于对事件队列中的事件进行条目，其中每个系统资源每个事件类型事件限制事件队列中预定数量的活动条目。 在特定实施例中，每个系统资源的每种类型的事件的条目数量被限制为一个。