公开(公告)号：US20050024068A1

公开(公告)日：2005-02-03

申请号：US10925337

申请日：2004-08-23

Applicant: Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

Inventor： Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

IPC: G01R1/04 ,  G01R27/26 ,  H01L29/40

CPC classification number: G01R31/04 ,  G01R1/0408 ,  G01R1/06772 ,  G01R27/2617 ,  G01R31/2896 ,  H01L24/73 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Apparatus and methods for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

Abstract translation: 使用网络分析仪结合同轴测试探针测量任何类型或配置的集成电路封装中的互耦合电位的装置和方法。 简单，低成本的测试夹具和测试方法可用于测量集成电路封装的一个或多个I / O引线的寄生电容和电感，所测量的寄生电容和电感提供了集成电路的易感性指示 电路封装以在封装的电引线之间或电引线和集成电路封装的其它部件之间相互耦合。

公开(公告)号：US06526519B1

公开(公告)日：2003-02-25

申请号：US09384192

申请日：1999-08-27

Applicant: David Cuthbert

Inventor： David Cuthbert

IPC: G06F104

CPC classification number: H05K1/0248 ,  G06F1/10 ,  H05K1/0293 ,  H05K3/027 ,  H05K2201/09263 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/0979 ,  H05K2203/095 ,  H05K2203/107 ,  H05K2203/1115 ,  H05K2203/1338 ,  H05K2203/171 ,  H05K2203/175

Abstract: An apparatus and method are described for reducing the timing skew on a printed circuit board including a plurality of conductive traces interconnecting a first node and a second node. At least one section is removed from at least one printed circuit board trace to thereby sever a trace and prevent signals passing from the first node to the second node from following the severed trace. In this manner, signal path length can be adjusted to reduce timing skews in the circuit. Sections are removed from the traces by using a laser, CVD, a router, a plasma or by passing sufficient current through weakened areas of the traces.

Abstract translation: 描述了一种用于减少包括互连第一节点和第二节点的多个导电迹线的印刷电路板上的定时偏移的装置和方法。 至少一个部分从至少一个印刷电路板迹线移除，从而切断迹线并防止从第一节点传递到第二节点的信号不跟随切断的迹线。 以这种方式，可以调整信号路径长度以减少电路中的定时偏差。 通过使用激光，CVD，路由器，等离子体或者通过使足够的电流通过弱化区域从迹线中去除部分。