公开(公告)号：US20060043987A1

公开(公告)日：2006-03-02

申请号：US11269047

申请日：2005-11-07

申请人： Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

发明人： Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

IPC分类号： G01R31/02

CPC分类号： G01R31/04 ,  G01R1/0408 ,  G01R1/06772 ,  G01R27/2617 ,  G01R31/2896 ,  H01L24/73 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： Methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

摘要翻译： 提供了用于使用网络分析仪与同轴测试探针一起测量任何类型或配置的集成电路封装中的互耦合的可能性的方法。 简单，低成本的测试夹具和测试方法可用于测量集成电路封装的一个或多个I / O引线的寄生电容和电感，所测量的寄生电容和电感提供了集成电路的易感性指示 电路封装以在封装的电引线之间或电引线和集成电路封装的其它部件之间相互耦合。

公开(公告)号：US20050161801A1

公开(公告)日：2005-07-28

申请号：US11083591

申请日：2005-03-18

申请人： Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

发明人： Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

IPC分类号： G01R1/04 ,  G01R27/26 ,  H01L23/52

CPC分类号： G01R31/04 ,  G01R1/0408 ,  G01R1/06772 ,  G01R27/2617 ,  G01R31/2896 ,  H01L24/73 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

公开(公告)号：US20050024068A1

公开(公告)日：2005-02-03

申请号：US10925337

申请日：2004-08-23

申请人： Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

发明人： Mark Van Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

IPC分类号： G01R1/04 ,  G01R27/26 ,  H01L29/40

CPC分类号： G01R31/04 ,  G01R1/0408 ,  G01R1/06772 ,  G01R27/2617 ,  G01R31/2896 ,  H01L24/73 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： Apparatus and methods for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

摘要翻译： 使用网络分析仪结合同轴测试探针测量任何类型或配置的集成电路封装中的互耦合电位的装置和方法。 简单，低成本的测试夹具和测试方法可用于测量集成电路封装的一个或多个I / O引线的寄生电容和电感，所测量的寄生电容和电感提供了集成电路的易感性指示 电路封装以在封装的电引线之间或电引线和集成电路封装的其它部件之间相互耦合。

公开(公告)号：US20050161256A1

公开(公告)日：2005-07-28

申请号：US11083506

申请日：2005-03-18

申请人： Mark Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

发明人： Mark Horn ,  Richard Hedden ,  David Cuthbert ,  Aaron Schoenfeld

IPC分类号： G01R1/04 ,  G01R27/26 ,  H05K1/11 ,  H01R12/04

CPC分类号： G01R31/04 ,  G01R1/0408 ,  G01R1/06772 ,  G01R27/2617 ,  G01R31/2896 ,  H01L24/73 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

摘要翻译： 提供了装置和方法，用于使用网络分析仪结合同轴测试探针来测量任何类型或配置的集成电路封装中的互耦合的可能性。 简单，低成本的测试夹具和测试方法可用于测量集成电路封装的一个或多个I / O引线的寄生电容和电感，所测量的寄生电容和电感提供了集成电路的易感性指示 电路封装以在封装的电引线之间或电引线和集成电路封装的其它部件之间相互耦合。

公开(公告)号：US06675313B2

公开(公告)日：2004-01-06

申请号：US10329494

申请日：2002-12-27

申请人： David Cuthbert

发明人： David Cuthbert

IPC分类号： G06F104

CPC分类号： H05K1/0248 ,  G06F1/10 ,  H05K1/0293 ,  H05K3/027 ,  H05K2201/09263 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/0979 ,  H05K2203/095 ,  H05K2203/107 ,  H05K2203/1115 ,  H05K2203/1338 ,  H05K2203/171 ,  H05K2203/175

摘要： An apparatus and method are described for reducing the timing skew on a printed circuit board including a plurality of conductive traces interconnecting a first node and a second node. At least one section is removed from at least one printed circuit board trace to thereby sever a trace and prevent signals passing from the first node to the second node from following the severed trace. In this manner, signal path length can be adjusted to reduce timing skews in the circuit. Sections are removed from the traces by using a laser, CVD, a router, a plasma or by passing sufficient current through weakened areas of the traces.

摘要翻译： 描述了一种用于减少包括互连第一节点和第二节点的多个导电迹线的印刷电路板上的定时偏移的装置和方法。 至少一个部分从至少一个印刷电路板迹线移除，从而切断迹线并防止从第一节点传递到第二节点的信号不跟随切断的迹线。 以这种方式，可以调整信号路径长度以减少电路中的定时偏差。 通过使用激光，CVD，路由器，等离子体或者通过使足够的电流通过弱化区域从迹线中去除部分。

公开(公告)号：US20070054550A1

公开(公告)日：2007-03-08

申请号：US11278541

申请日：2006-04-03

申请人： David Cuthbert ,  Larry Rogel ,  Matthew Page ,  James Page

发明人： David Cuthbert ,  Larry Rogel ,  Matthew Page ,  James Page

IPC分类号： H01R13/648

CPC分类号： H01R29/00 ,  H01R27/02 ,  H01R2201/04 ,  H01R2201/06

摘要： An apparatus which provides the ability to charge or power multiple devices from multiple different power sources, and to communicate electronic data to and from one of the devices. The apparatus utilizes simple construction, requiring no active electronics, thereby reducing the cost of production and the reliability of the device. The apparatus employs a single USB connection cable with connectors on both ends and a second power-only cable and connector which is connected to the power wires of the USB cable and thereby is able to power a second portable device from a single USB port. USB master provide sufficient power for two average portable devices without additional circuitry. Moreover, restricting the data path to only one device also eliminates the need for USB hub circuitry. Finally, greater end user flexibility is provided by using a USB male connector as the source of the data and power connection, a USB female connector for the output of the data and power connection, and a standard barrel-type power connector for the power-only output connection. Having two different output connectors ensures that the user will not confuse the two connectors.

摘要翻译： 一种提供从多个不同电源对多个设备进行充电或供电的能力以及将电子数据传送到设备之一或从设备之一传送电子数据的设备。 该设备采用简单的结构，不需要有源电子元件，从而降低了生产成本和设备的可靠性。 该装置采用单个USB连接电缆，其两端具有连接器，以及第二电源电缆和连接器，其连接到USB电缆的电源线，从而能够从单个USB端口为第二便携式设备供电。 USB主机为两个平均的便携式设备提供足够的电力，无需额外的电路。 而且，将数据路径限制在一个设备上也不需要USB集线器电路。 最后，通过使用USB公连接器作为数据和电源连接的来源，提供用于输出数据和电源连接的USB母连接器以及用于电源连接的标准机筒式电源连接器来提供更大的终端用户灵活性， 只输出连接。 具有两个不同的输出连接器可确保用户不会混淆两个连接器。

公开(公告)号：US20050206400A1

公开(公告)日：2005-09-22

申请号：US11142226

申请日：2005-06-01

申请人： William Casey ,  David Cuthbert ,  Olivia McGrew

发明人： William Casey ,  David Cuthbert ,  Olivia McGrew

IPC分类号： G01R31/28 ,  H05K1/02 ,  H05K1/11 ,  G01R31/02

CPC分类号： H05K1/0268 ,  G01R31/2889 ,  H05K1/112 ,  H05K2201/09781

摘要： An integrated circuit characterization printed circuit board and method are provided for improving the uniformity of impedance introduced by a test fixture across all of the pins of an integrated circuit device. The printed circuit board includes an array of substantially similar test contacts numbering greater than the pins of the integrated circuit device. The array of test contacts includes an active portion configured for electrically coupling with the corresponding pins on the integrated circuit device and an inactive portion adjacent to the active portion and electrically coupled to a reference signal on the printed circuit board.

摘要翻译： 提供了一种集成电路表征印刷电路板和方法，用于改善由集成电路器件的所有引脚上的测试夹具引入的阻抗的均匀性。 印刷电路板包括大致类似的测试触头的阵列，编号大于集成电路器件的引脚。 测试触点阵列包括被配置用于与集成电路器件上的相应引脚电耦合的有源部分和与有源部分相邻的非活动部分，并电耦合到印刷电路板上的参考信号。

公开(公告)号：US20060291312A1

公开(公告)日：2006-12-28

申请号：US11494027

申请日：2006-07-27

申请人： Leonard Forbes ,  David Cuthbert

发明人： Leonard Forbes ,  David Cuthbert

IPC分类号： G11C7/02

CPC分类号： H03F3/45183 ,  H03F1/08 ,  H03F1/14 ,  H03F3/45273 ,  H03F2203/45264 ,  H03F2203/45332

摘要： The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

摘要翻译： CMOS差分放大器的频率和瞬态响应通过采用一个或多个补偿电容来改善。 耦合到CMOS差分放大器的差分输入的补偿电容器用于将电流注入到差分输入端中，使得通过MOS输入晶体管的栅 - 漏电容的净电流流过零。 因此，相对于该MOS输入晶体管的米勒效应被显着降低或消除，导致CMOS差分放大器的频率和瞬态响应增加。 在一个实施例中，CMOS差分放大器是CMOS电流镜差分放大器。

公开(公告)号：US20060268140A1

公开(公告)日：2006-11-30

申请号：US11135520

申请日：2005-05-24

申请人： Leonard Forbes ,  David Cuthbert

发明人： Leonard Forbes ,  David Cuthbert

IPC分类号： H04N5/335

CPC分类号： H04N5/378 ,  H04N5/3575 ,  H04N5/3651

摘要： A technique for reducing 1/f noise in an imager, in which the source follower transistor in a pixel circuit is turned off prior to a correlated double sampling (CDS) operation, thereby reducing 1/f noise in the source follower transistor for up to 100 ms. The source follower transistor is then reactivated and a CDS operation and readout is performed normally. This technique substantially reduces the contributions of 1/f noise. The invention also provides a reduction of 1/f noise in an analog amplifier circuit which may process pixel output signals, or more generally, other analog signals, whereby the analog amplifier is turned off during an amplifier reset operation prior to signal amplification. The analog amplifier circuit may be a differential amplifier or a switched capacitor analog amplifier circuit.

摘要翻译： 用于降低成像器中1 / f噪声的技术，其中像素电路中的源极跟随器晶体管在相关双采样（CDS）操作之前被截止，从而减少源极跟随器晶体管中的1 / f噪声，直到 100毫秒 源极跟随器晶体管然后被重新激活，并且正常执行CDS操作和读出。 该技术大大降低了1 / f噪声的贡献。 本发明还提供可以处理像素输出信号或更一般地，其它模拟信号的模拟放大器电路中的1 / f噪声的减小，由此在信号放大之前的放大器复位操作期间模拟放大器被关断。 模拟放大器电路可以是差分放大器或开关电容器模拟放大器电路。

公开(公告)号：US20060261896A1

公开(公告)日：2006-11-23

申请号：US11493966

申请日：2006-07-27

申请人： Leonard Forbes ,  David Cuthbert

发明人： Leonard Forbes ,  David Cuthbert

IPC分类号： H03F1/14

CPC分类号： H03F3/45183 ,  H03F1/08 ,  H03F1/14 ,  H03F3/45273 ,  H03F2203/45264 ,  H03F2203/45332

摘要： The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.