公开(公告)号：US20190098759A1

公开(公告)日：2019-03-28

申请号：US16135982

申请日：2018-09-19

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： Richard Austin Blanchard ,  William Johnstone Ray

IPC: H05K1/16 ,  H01L29/06 ,  H05K1/02 ,  H01L21/77 ,  H01L21/02 ,  H05K3/12 ,  H01L29/40

CPC classification number: H05K1/16 ,  H01L21/02288 ,  H01L21/561 ,  H01L21/77 ,  H01L22/22 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L29/0646 ,  H01L29/401 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29499 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/8284 ,  H01L2224/83192 ,  H01L2224/8384 ,  H01L2224/95101 ,  H01L2224/95102 ,  H01L2224/95146 ,  H01L2224/97 ,  H03K19/017581 ,  H03K19/08 ,  H05K1/0293 ,  H05K1/189 ,  H05K3/12 ,  H05K3/30 ,  H05K2201/026 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2203/0783 ,  H05K2203/1115 ,  H05K2203/175 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00014

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes having pn junctions. The devices are pre-formed and printed as an ink and cured. The devices have a proper orientation and a reverse orientation after settling on a conductor layer. The devices are connected in parallel within small groups. To neutralize the reverse-oriented devices, a sufficient voltage is applied across the parallel-connected diodes to forward bias only the devices having the reverse orientation. This causes a sufficient current to flow through each of the reverse-orientated devices to destroy an electrical interface between an electrode of the devices and the conductor layer to create an open circuit, such that those devices do not affect a rectifying function of the devices in the group having the proper orientation. An interconnection conductor pattern may then interconnect the groups to form complex logic circuits.

公开(公告)号：US09977074B2

公开(公告)日：2018-05-22

申请号：US14672611

申请日：2015-03-30

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Tomoharu Fujii

IPC: H05K7/10 ,  H05K7/12 ,  G01R31/28 ,  H05K1/02 ,  H05K3/00 ,  H01L23/00

CPC classification number: G01R31/2818 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/19105 ,  H05K1/0268 ,  H05K3/0052 ,  H05K2201/09036 ,  H05K2201/09127 ,  H05K2201/0989 ,  H05K2201/09972 ,  H05K2203/175

Abstract: A semiconductor device includes a board, an electronic component, an evaluation component, a wiring, and a groove portion. The board includes a product area, a non-product area, and a boundary area between the product area and the non-product area. The electronic component is mounted in the product area. The evaluation component is mounted in the non-product area. The wiring electrically connects the electronic component and the evaluation component. The groove portion is formed in the boundary area of the board so as to overlap at least a part of the wiring in a plan view. The non-product area is surrounded by the groove portion and at least a portion of sides of the board.

公开(公告)号：US09907172B2

公开(公告)日：2018-02-27

申请号：US14033776

申请日：2013-09-23

Applicant: Control Techniques Limited

Inventor： Stephen Berry

IPC: H05K1/16 ,  H05K1/18 ,  H01G2/16 ,  H01G4/38 ,  H05K1/02

CPC classification number: H05K1/18 ,  H01G2/16 ,  H01G4/38 ,  H05K1/0263 ,  H05K1/0293 ,  H05K2201/10015 ,  H05K2203/175

Abstract: A capacitor bank comprising at least two series chains each comprising a plurality of capacitors, wherein the series chains are coupled in parallel at corresponding points; and a fusible link arranged to form at least part of each coupling; wherein the corresponding points of each chain that are coupled to one another are at the same voltage when the capacitor bank is operational.

公开(公告)号：US09826634B2

公开(公告)日：2017-11-21

申请号：US14345352

申请日：2012-11-27

Applicant: Taiwan Green Point Enterprises Co., Ltd.

Inventor： Sheng-Hung Yi ,  Pen-Yi Liao ,  Min-Hsiang Chen

IPC: H05K1/09 ,  H05K3/02 ,  H05K3/24 ,  H05K1/02 ,  H05K3/38 ,  H05K3/18

CPC classification number: H05K1/09 ,  H05K1/0296 ,  H05K3/027 ,  H05K3/182 ,  H05K3/188 ,  H05K3/242 ,  H05K3/243 ,  H05K3/381 ,  H05K2201/0116 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/108 ,  H05K2203/175

Abstract: A method for fabricating a conductive trace structure includes the steps: forming a first metal layer on a non-conductive substrate; removing a part of the first metal layer to expose the non-conductive substrate so as to form the first metal layer into a plating region and a non-plating region, the plating region being divided into at least two trace-forming portions and at least one bridge portion; forming a second metal layer on the plating region by electroplating the plating region using one of the trace-forming portions and the bridge portion as an electrode; and removing the bridge portion and the second metal layer formed on the bridge portion.

公开(公告)号：US09699896B2

公开(公告)日：2017-07-04

申请号：US14792878

申请日：2015-07-07

Applicant: SEIKO EPSON CORPORATION

Inventor： Hideki Takahashi

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/029 ,  H05K1/0286 ,  H05K1/0296 ,  H05K1/11 ,  H05K1/181 ,  H05K1/184 ,  H05K2201/093 ,  H05K2203/175

Abstract: A substrate includes a first pattern on which terminals are formed; a second pattern on which terminals are formed; and a third pattern on which terminals are formed. A distance between a first pair of terminals which are configured by one terminal of the first pattern and one terminal of the second pattern is equal to a distance between a second pair of terminals which are configured by another terminal of the first pattern and one terminal of the third pattern, and a distance between a third pair of terminals which are configured by another of the terminals of the third pattern and another of the terminals of the second pattern is equal to a distance between a fourth pair of terminals which are configured by the other of the terminal of the third pattern and the other of the terminal of the first pattern.

公开(公告)号：US20170164482A1

公开(公告)日：2017-06-08

申请号：US15351234

申请日：2016-11-14

Applicant: The Board of Trustees of the University of Illinois

Inventor： John A. ROGERS ,  Seung-Kyun KANG ,  SukWon HWANG ,  Jianjun CHENG ,  Yanfeng ZHANG ,  Hanze YING

IPC: H05K1/18 ,  H05K3/28 ,  H05K1/03 ,  H01L25/065 ,  A61B5/00 ,  H01L23/29 ,  H01L23/498 ,  H01L21/56 ,  H01L21/02 ,  H01L21/311 ,  G06K19/077 ,  H01L23/31

CPC classification number: H05K1/185 ,  A61B5/686 ,  A61B2562/125 ,  A61M5/44 ,  G06K19/0775 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/49894 ,  H01L25/0655 ,  H01L2924/0002 ,  H05K1/0275 ,  H05K1/0286 ,  H05K1/0306 ,  H05K3/22 ,  H05K3/285 ,  H05K3/287 ,  H05K3/288 ,  H05K5/069 ,  H05K13/00 ,  H05K2201/10151 ,  H05K2201/10196 ,  H05K2201/10212 ,  H05K2203/0271 ,  H05K2203/0292 ,  H05K2203/0769 ,  H05K2203/0776 ,  H05K2203/0786 ,  H05K2203/17 ,  H05K2203/175 ,  H05K2203/178 ,  Y10T29/49124 ,  Y10T137/0318 ,  Y10T428/239 ,  H01L2924/00

Abstract: The invention provides transient devices, including active and passive devices that physically, chemically and/or electrically transform upon application of at least one internal and/or external stimulus. Incorporation of degradable device components, degradable substrates and/or degradable encapsulating materials each having a programmable, controllable and/or selectable degradation rate provides a means of transforming the device. In some embodiments, for example, transient devices of the invention combine degradable high performance single crystalline inorganic materials with selectively removable substrates and/or encapsulants.

公开(公告)号：US09521751B2

公开(公告)日：2016-12-13

申请号：US14085613

申请日：2013-11-20

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H01B7/00 ,  H01B3/50 ,  H05K1/16 ,  H01B7/08 ,  H01B3/48 ,  H01F17/00 ,  H05K1/03 ,  H05K3/10 ,  H05K3/40 ,  H01B3/04 ,  H01B7/02 ,  H05K1/02 ,  H05K3/04 ,  H05K3/26

CPC classification number: H05K3/10 ,  H01B3/485 ,  H01B3/50 ,  H01B7/083 ,  H01F17/0006 ,  H05K1/0222 ,  H05K1/038 ,  H05K1/165 ,  H05K3/043 ,  H05K3/103 ,  H05K3/22 ,  H05K3/26 ,  H05K3/30 ,  H05K3/40 ,  H05K3/4046 ,  H05K2201/029 ,  H05K2201/097 ,  H05K2201/09809 ,  H05K2201/10287 ,  H05K2201/1081 ,  H05K2203/0228 ,  H05K2203/025 ,  H05K2203/1461 ,  H05K2203/175 ,  H05K2203/30

Abstract: A substrate package includes a woven fabric having electrically non-conductive strands woven between electrically conductive strands including wire strands, co-axial strands, and/or an inductor pattern of strands. The package may be formed by an inexpensive and high throughput process that first weaves the non-conductive strands (e.g., glass) between the conductive strands to form a circuit board pattern of conductive strands in a woven fabric. Next, the woven fabric is impregnated with a resin material to form an impregnated fabric, which is then cured to form a cured fabric. The upper and lower surfaces of the cured fabric are subsequently planarized. Planarizing segments and exposes ends of the wire, co-axial, and inductor pattern strands. Since the conductive strands were formed integrally within the planarized woven fabric, the substrate has a high mechanical stability and provides conductor strand based electrical components built in situ in the substrate package.

Abstract translation: 衬底封装包括织造织物，其具有在导电股线之间编织的非导电股线，包括线股，同轴股线和/或股线的电感器图案。 封装可以通过廉价且高通量的工艺来形成，该工艺首先在导电股线之间编织非导电股线（例如玻璃），以形成机织织物中导电股线的电路板图案。 接下来，用树脂材料浸渍织物以形成浸渍织物，然后将其固化以形成固化织物。 随后将固化的织物的上表面和下表面平坦化。 平面化节段并露出导线，同轴和电感图案线的端部。 由于导电丝线整体地形成在平面织造织物内，所以基底具有高的机械稳定性，并提供了在基底包装中原位构建的基于导线的电气部件。

公开(公告)号：US20160338204A1

公开(公告)日：2016-11-17

申请号：US15112644

申请日：2015-01-20

Applicant: SMART WAVE TECHNOLOGIES CORP.

Inventor： Scott Arthur McMullen ,  Peter Zosimadis

IPC: H05K3/00 ,  B23K26/351 ,  B23K26/38 ,  H05K1/02

CPC classification number: H05K3/0052 ,  B23K26/351 ,  B23K26/38 ,  B23K2101/42 ,  H05K1/0269 ,  H05K1/0292 ,  H05K3/0097 ,  H05K3/26 ,  H05K2201/09936 ,  H05K2203/081 ,  H05K2203/108 ,  H05K2203/171 ,  H05K2203/175 ,  H05K2203/178

Abstract: A method for processing a PCBa panel to individualize the PCBa's on the PCBa panel and depanel the PCBa panel in substantially one step is described. The PCBa panel initially comprises a number of PCBa's having components and traces common to a number of different product SKUs. During processing, the PCBa panel is loaded into a machine containing a first and second laser. The first laser severs extra traces on each PCBa to individualize the PCBa's for specific SKUs and the second laser cuts the links between each PCBa, thereby depaneling the PCBa panel.

Abstract translation: 描述了用于处理PCBa面板以在PCBa面板上个性化PCBa并且基本上一步地去除PCBa面板的方法。 PCBa面板最初包括许多PCBa具有许多不同产品SKU通用的组件和痕迹。 在处理过程中，PCBa面板装入包含第一和第二激光器的机器中。 第一台激光切割每个PCBa上的额外痕迹，以使PCBa的特定SKU个性化，第二个激光切割每个PCBa之间的连接，从而拆卸PCBa面板。

公开(公告)号：US09368183B2

公开(公告)日：2016-06-14

申请号：US13938117

申请日：2013-07-09

Applicant: NVIDIA CORPORATION

Inventor： Leilei Zhang

IPC: H01L21/445 ,  G11C11/34 ,  H05K3/24 ,  H01L21/48 ,  H05K3/06

CPC classification number: G11C11/34 ,  H01L21/48 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H05K3/067 ,  H05K3/242 ,  H05K2203/175 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated circuit package includes a packaging substrate with an electrical connection pad formed thereon and an integrated circuit die coupled to the electrical connection pad. The electrical connection pad includes an electroplated surface finish layer, but does not include an electrical trace configured as a plating tail. Because the electrical connection pad is free of a plating tail, signal degradation caused by the presence of plating tails in the integrated circuit package is avoided.

Abstract translation: 集成电路封装包括其上形成有电连接焊盘的封装衬底和耦合到电连接焊盘的集成电路裸片。 电连接焊盘包括电镀表面光洁度层，但不包括构造为电镀尾部的电迹线。 由于电连接垫没有电镀尾部，所以避免了由集成电路封装中的电镀尾部引起的信号劣化。

公开(公告)号：US09232629B2

公开(公告)日：2016-01-05

申请号：US13564503

申请日：2012-08-01

Applicant: Shinichi Jingama ,  Kengo Aburaya ,  Hideki Nakazato ,  Kazumasa Sakata ,  Shinya Saito

Inventor： Shinichi Jingama ,  Kengo Aburaya ,  Hideki Nakazato ,  Kazumasa Sakata ,  Shinya Saito

IPC: H05K1/00 ,  H05K1/02 ,  H05K3/44

CPC classification number: H05K1/0203 ,  H05K3/44 ,  H05K2201/09972 ,  H05K2203/0242 ,  H05K2203/175

Abstract: Provided is a metal core board which has a preferable function for a vehicle-mountable junction box, specifically, is reduced in size or improved in mounting efficiency. A metal core board for a vehicle-mountable junction box, which is mountable on the vehicle-mountable junction box, wherein a core plate forming an intermediate layer of the metal core board has a plurality of slits and an island surrounded by separating connection parts present between the slits; and in the state where the island is held between insulating layers stacked on both of two surfaces of the core plate, through-bores 46 are formed at the separating connection parts to remove the separating connection parts and the island is made electrically independent from a remaining part of the core plate while being held between the insulating layers. Thus, a plurality of circuits can be formed.

Abstract translation: 本发明提供一种对车载接线盒具有优选功能的金属芯板，具体地说是减小了尺寸或提高了安装效率。 一种用于车载接线盒的金属芯板，其可安装在车载接线盒上，其中形成金属芯板的中间层的芯板具有多个狭缝和由分离的连接部分所包围的岛状物 在狭缝之间; 并且在岛被保持在堆叠在芯板的两个表面的绝缘层之间的状态下，在分离连接部分处形成通孔46以去除分离连接部分，并且使岛与剩余的电气独立 夹持在绝缘层之间的芯板的一部分。 因此，可以形成多个电路。