公开(公告)号：US09117815B2

公开(公告)日：2015-08-25

申请号：US13777757

申请日：2013-02-26

申请人： Marvell World Trade Ltd.

发明人： Sehat Sutardja

IPC分类号： H01R43/00 ,  H01L21/50 ,  H01L23/495 ,  H01L23/00

CPC分类号： H01L21/50 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A method of fabricating a packaged semiconductor includes forming a conductive frame as an integral piece of conductive material. The frame includes an inner portion and a ring portion encircling the inner portion. The ring portion includes a first ring portion encircling first and second sides of the inner portion, and a first bar portion located on a third side of the inner portion. The method includes mounting a semiconductor die to a first surface of the inner portion of the frame. The die is configured to receive power via the first ring portion. The method includes applying a casing, which covers the die, to the frame. The method includes, after the casing is applied to the frame, removing (i) sections of the frame that connect the inner portion to the ring portion, and (ii) sections of the frame that connect the first ring portion to the first bar portion.

摘要翻译： 制造封装半导体的方法包括形成导电框架作为导电材料的整体。 框架包括内部部分和环绕内部部分的环形部分。 环部包括环绕内部的第一和第二侧的第一环部分和位于内部部分的第三侧上的第一杆部分。 该方法包括将半导体管芯安装到框架内部的第一表面。 模具被配置成经由第一环部分接收电力。 该方法包括将覆盖模具的壳体应用于框架。 该方法包括：在壳体被施加到框架之后，移除（i）将内部部分连接到环部分的框架部分，以及（ii）将第一环部分连接到第一杆部分的框架部分 。

公开(公告)号：US08922028B2

公开(公告)日：2014-12-30

申请号：US13088117

申请日：2011-04-15

申请人： Sung-Ching Hung ,  Wen-Pin Huang

发明人： Sung-Ching Hung ,  Wen-Pin Huang

IPC分类号： H01L23/495 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/50

CPC分类号： H01L23/13 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32233 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49505 ,  H01L2224/73265 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention relates to a semiconductor package, comprising a carrier, a semiconductor device, a first wire and a second wire. The carrier has a first electrically connecting portion and a second electrically connecting portion. The semiconductor device has a plurality of pads. The first wire electrically connects one of the pads of the semiconductor device and the first electrically connecting portion of the carrier, and the first wire has a first length. The second wire electrically connects one of the pads of the semiconductor device and the second electrically connecting portion of the carrier, and the second wire has a second length. The second length is larger than the first length, and the diameter of the second wire is larger than that of the first wire. Thus, the material usage for the wire is reduced, and the manufacturing cost is reduced.

摘要翻译： 本发明涉及一种半导体封装，包括载体，半导体器件，第一布线和第二布线。 载体具有第一电连接部分和第二电连接部分。 半导体器件具有多个焊盘。 第一线将半导体器件的焊盘和载体的第一电连接部分之一电连接，并且第一焊丝具有第一长度。 第二线电连接半导体器件的焊盘之一和载体的第二电连接部分，并且第二导线具有第二长度。 第二长度大于第一长度，并且第二线的直径大于第一线的直径。 因此，电线的材料使用减少，制造成本降低。

公开(公告)号：US20140054692A1

公开(公告)日：2014-02-27

申请号：US14072047

申请日：2013-11-05

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki SHIRAISHI ,  Tomoaki UNO ,  Nobuyoshi MATSUURA

IPC分类号： H01L29/78

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

摘要翻译： 在具有电源MOS.FET高侧开关和功率MOS.FET低侧开关串联连接的电路的非绝缘DC-DC转换器中，功率MOS.FET低侧开关和肖特基 与功率MOS.FET低侧开关并联连接的阻挡二极管形成在一个半导体芯片内。 肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中心，并且在其两侧设置功率MOS.FET低侧开关的形成区域。 从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

公开(公告)号：US08519533B2

公开(公告)日：2013-08-27

申请号：US13396073

申请日：2012-02-14

申请人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

发明人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

IPC分类号： H01L23/34

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

摘要翻译： 在具有电源MOS.FET高侧开关和功率MOS.FET低侧开关串联连接的电路的非绝缘DC-DC转换器中，功率MOS.FET低侧开关和肖特基 与功率MOS.FET低侧开关并联连接的阻挡二极管形成在一个半导体芯片内。 肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中心，并且在其两侧设置功率MOS.FET低侧开关的形成区域。 从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

公开(公告)号：US08482112B1

公开(公告)日：2013-07-09

申请号：US13234390

申请日：2011-09-16

申请人： Shiann-Ming Liou ,  Chenglin Liu

发明人： Shiann-Ming Liou ,  Chenglin Liu

IPC分类号： H01L23/02

CPC分类号： H01L23/49575 ,  H01L21/50 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49537 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49425 ,  H01L2224/49429 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package is provided and methods for bonding wires in the semiconductor package. In one implementation, the semiconductor package includes a lead frame including a first die pad and a second die pad; each die pad is supported by one or more supports and isolated from another; at least first and second dice, a first die being disposed on the first die pad and a second die being disposed on the second die pad; wire bonds in communication with the first and second dice; and an encapsulant adapted to encapsulate the die pads, the dice, the lead frame and the wire bonds.

摘要翻译： 提供一种半导体封装以及用于在半导体封装中接合引线的方法。 在一个实施方式中，半导体封装包括包括第一管芯焊盘和第二管芯焊盘的引线框架; 每个管芯焊盘由一个或多个支撑件支撑并与另一个支撑隔离; 至少第一和第二骰子，第一管芯设置在第一管芯焊盘上，第二管芯设置在第二管芯焊盘上; 与第一和第二骰子通信的电线键; 以及适于封装管芯焊盘，裸片，引线框架和引线接合的密封剂。

公开(公告)号：US08441110B1

公开(公告)日：2013-05-14

申请号：US13109845

申请日：2011-05-17

申请人： Yeon Ho Choi

发明人： Yeon Ho Choi

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49558 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.

摘要翻译： 一种半导体封装，其包括限定多个外围边缘段的大致平坦的管芯焊盘和分离成至少两个同心的行的多个引线。 连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到每行的至少一些引线。 芯片，引线和半导体管芯的至少一部分被封装体封装，裸片焊盘的底表面和至少一排的引线暴露在封装主体的公共外表面中。

公开(公告)号：US08126501B2

公开(公告)日：2012-02-28

申请号：US13094383

申请日：2011-04-26

申请人： Tadatoshi Danno ,  Tsutomu Tsuchiya

发明人： Tadatoshi Danno ,  Tsutomu Tsuchiya

IPC分类号： H04M1/00 ,  H04B1/28

CPC分类号： H01L24/32 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/50 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/29007 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H03F3/189 ,  H01L2924/20645 ,  H01L2224/83 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab. In such a semiconductor device, a circuit formed in the semiconductor element in a monolithic manner is comprised of a plurality of circuit parts and, in a specified circuit part (a low noise amplifier) which forms a portion of the circuit parts, all grounding electrode terminals out of electrode terminals of the semiconductor element are not connected to the tab through wires but are connected with the leads through wires.

摘要翻译： 本发明提供一种并入移动电话中的高频功率模块，其包括高频部分模拟信号处理IC，包括放大其中极弱信号的低噪声放大器。 一种半导体器件，包括由绝缘树脂制成的密封体，设置在密封体的内部和外部的多个引线，设置在密封体内部并具有半导体元件固定区域和导线连接区域的突片 其主表面，固定到半导体元件固定区并且在暴露的主表面上包括电极端子的半导体元件，连接半导体元件的电极端子和引线的导线以及连接半导体元件的电极端子的导线 半导体元件和引线连接区域。 在这种半导体装置中，以单片方式形成在半导体元件中的电路由多个电路部分构成，并且在形成电路部分的一部分的规定电路部分（低噪声放大器）中，所有接地极 半导体元件的电极端子之外的端子不通过导线连接到突片，而是通过导线与引线连接。

公开(公告)号：US08124447B2

公开(公告)日：2012-02-28

申请号：US12547787

申请日：2009-08-26

申请人： Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Po-Shing Chiang ,  Wei-Lun Cheng

发明人： Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Po-Shing Chiang ,  Wei-Lun Cheng

IPC分类号： H01L21/00

CPC分类号： H01L21/4832 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/28 ,  H01L24/48 ,  H01L24/92 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： The manufacturing method of advanced quad flat non-leaded packages includes performing a pre-cutting process prior to the backside etching process for defining the contact terminals. The pre-cutting process ensures the isolation of individual contact terminals and improves the package reliability.

摘要翻译： 先进的四边形扁平非铅封装的制造方法包括在用于限定接触端子的背面蚀刻工艺之前执行预切割工艺。 预切割过程确保了单个接触端子的隔离，并提高了封装的可靠性。

公开(公告)号：US08039933B2

公开(公告)日：2011-10-18

申请号：US12840304

申请日：2010-07-21

申请人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

发明人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49586 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a third wire bonding the intermediary terminal to the extended, outer terminal lead.

摘要翻译： QFN半导体封装包括管芯附接垫; 安装在管芯附接垫上的半导体管芯; 设置在所述管芯附接垫附近的内部端子引线; 将内部端子引线接合到半导体管芯的第一引线; 延伸的外部端子引线，设置在所述QFN半导体封装的周围，其中所述延伸的外部端子引线设置在超过所述半导体管芯上的特定最小焊盘开口尺寸的最大焊丝长度之上; 设置在内端子引线和延伸外端子引线之间的中间端子; 将所述中间端子连接到所述半导体管芯的第二引线; 以及将中间终端连接到扩展的外部终端引线的第三引线。

公开(公告)号：US07986032B2

公开(公告)日：2011-07-26

申请号：US12547439

申请日：2009-08-25

申请人： Seng Guan Chow ,  Ming Ying ,  Ii Kwon Shim ,  Lip Seng Tan

发明人： Seng Guan Chow ,  Ming Ying ,  Ii Kwon Shim ,  Lip Seng Tan

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49109 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package system is provided. A substrate having a die attach paddle is provided. A first plurality of leads is provided around the die attach paddle having a first plurality of lead tips. A second plurality of leads is provided around the die attach paddle interleaved with the first plurality of leads, at least some of the second plurality of leads having a plurality of depression lead tips. A first die is attached to the die attach paddle. The die is wire bonded to the first plurality of leads and the second plurality of leads. The die is encapsulated.

摘要翻译： 提供半导体封装系统。 提供具有管芯附接板的衬底。 第一组多个引线设置在具有第一多个引线端的管芯附接焊盘的周围。 第二多个引线设置在与第一多个引线交错的管芯附接焊盘周围，第二多个引线中的至少一些具有多个凹陷引线尖端。 第一管芯附接到管芯附接板上。 模具被引线接合到第一多个引线和第二多个引线。 模具被封装。