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公开(公告)号：US20120124421A1
公开(公告)日：2012-05-17
申请号：US12926436
申请日：2010-11-17
IPC分类号： G06F11/07
CPC分类号： G06F11/0763 , H03M13/09
摘要： A data processing system 2 is used to perform processing operations to generate a result value. The processing circuitry which generates the result value has an error resistant portion 32 and an error prone portion 30. The probability of an error in operation of the error prone portion for a given set of operating parameters (clk, V) is greater than the probability of an error for that same set of operating parameters within the error resistant portion. Error detection circuitry 38 detects any errors arising in the error prone portion. Parameter control circuitry 40 responds to detected errors to adjust the set of operating parameters to maintain a non-zero error rate in the errors detected by the error detection circuitry. Errors within the one or more bits generated by the error prone portion are not corrected as the apparatus is tolerant to errors occurring within such bit values of the result value.
摘要翻译： 数据处理系统2用于执行处理操作以产生结果值。 产生结果值的处理电路具有抗错部分32和易错部分30.对于给定的一组操作参数（clk，V），错误倾向部分的操作错误的概率大于概率 在该抗误差部分内的相同的一组操作参数的误差。 错误检测电路38检测在易错部分中产生的任何错误。 参数控制电路40对检测到的错误进行响应，以调整该组操作参数，以便在错误检测电路检测到的错误中保持非零错误率。 由误差容易部分产生的一个或多个位内的错误不会被校正，因为该装置对结果值的这些比特值内发生的错误是容忍的。
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22.发明授权Error recovery following speculative execution with an instruction processing pipeline 有权使用指令处理流水线进行推测执行后出错恢复公开(公告)号：US08037287B2
公开(公告)日：2011-10-11
申请号：US12076165
申请日：2008-03-14
申请人： Emre Özer , Shidhartha Das , David Michael Bull
发明人： Emre Özer , Shidhartha Das , David Michael Bull
IPC分类号： G06F9/30
CPC分类号： G06F11/0793 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F11/0721
摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.
摘要翻译： 提供了指令处理流水线6。 这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 错误恢复的一部分可能是从指令流水线6冲洗上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令中刷新 流水线6.也可以根据诸如特权级别，依赖指令数量等特征来选择刷新指令。指令流水线可以另外地或替代地设置有多个主存储元件26,28，其与每个信号值相关联， 这些主存储元件26,28以交替的方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获对应于以下的信号值 程序指令。 这样可以避免冲洗。
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公开(公告)号：US08006147B2
公开(公告)日：2011-08-23
申请号：US12382427
申请日：2009-03-16
IPC分类号： G11C29/00
CPC分类号： G01R31/3177
摘要： An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.
摘要翻译： 集成电路提供有多米诺逻辑，包括推测节点和检查器节点。 预充电电路对推测节点和检查器节点进行预充电。 逻辑电路根据输入信号值为推测节点和校验器节点提供放电路径。 评估控制电路首先将推测节点耦合到逻辑电路，然后随后将校验器节点耦合到逻辑电路，使得如果逻辑电路的输入信号具有适当的值，则它们可以被放电。 当推测节点和检查器节点都不是放电或未放电的两者之一时，错误检测电路检测到错误。
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24.发明授权Data processing memory circuit having pull-down circuit with on/off configuration 有权数据处理存储器电路具有开/关配置的下拉电路公开(公告)号：US07855924B2
公开(公告)日：2010-12-21
申请号：US11436983
申请日：2006-05-19
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1012 , G11C7/12 , G11C29/1201 , G11C29/48 , G11C2207/108
摘要： A memory circuit includes a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. The memory circuit includes a pull-down circuit having an on configuration in which it is operable to pull-down a voltage level of at least one of the pair of conducting lines so as to affect the read operation and an off-configuration in which the pull-down circuit cannot affect the read operation. Control circuitry is configured to control whether the pull-down circuit is in the on configuration or the off configuration. The memory circuit can be incorporated in a data processing apparatus and a method of operating a memory circuit is provided in which a pull-down circuit is controlled to be in an on configuration or in an off configuration.
摘要翻译： 存储电路包括一个存储单元，一对导线，用于发信号通知存储单元的逻辑状态，读取电路可操作以通过检测一对导线中的至少一个的电压来执行读操作。 存储电路包括具有接通配置的下拉电路，其中其可操作以下拉一对导线中的至少一个的电压电平，以便影响读取操作，以及关闭配置，其中 下拉电路不能影响读操作。 控制电路被配置为控制下拉电路是处于接通配置还是断开配置。 存储器电路可以并入数据处理设备中，并且提供了一种操作存储器电路的方法，其中下拉电路被控制为处于接通配置或断开配置。
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公开(公告)号：US20090161442A1
公开(公告)日：2009-06-25
申请号：US12085901
申请日：2005-12-02
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/24 , G11C11/4125 , G11C29/12 , G11C29/12005 , G11C29/26
摘要： A data processing system comprising a memory array having a plurality of memory cells (240-246) and read circuitry (310,320) for reading a logic value stored in one of the plurality of memory cells. The read circuitry (310,320) is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided (330) for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.
摘要翻译： 一种数据处理系统，包括具有多个存储单元（240-246）和用于读取存储在所述多个存储单元之一中的逻辑值的读取电路（310,320）的存储器阵列。 读取电路（310,320）可操作地执行存储的逻辑值的两个基本上同时的读取。 提供电压控制器并且可操作以选择性地改变对存储器阵列的电源电压的电平。 提供检测电路（330），用于根据两个基本上同时的读取来检测供电电压电平是否导致读取结果不可靠。
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公开(公告)号：US20090106616A1
公开(公告)日：2009-04-23
申请号：US12285796
申请日：2008-10-14
申请人： Emre Ozer , David Michael Bull , Shidhartha Das
发明人： Emre Ozer , David Michael Bull , Shidhartha Das
IPC分类号： G06F11/07
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3869
摘要： An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.
摘要翻译： 集成电路2设置有多个流水线级10.这些流水线级10具有推测性处理控制电路12，其允许下游流水线级的推测性处理，并且如果确定了这种推测性处理，则触发第一错误恢复操作（部分流水线冲洗） 基于错误。 流水线级10还包括推测性错误检测电路14，其产生关于处理电路18是否将产生错误的预测nc。 该预测用于触发第二次错误恢复操作（部分流水线停止）。 该第二错误恢复操作具有比第一错误恢复操作更低的性能损失。
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公开(公告)号：US20080086624A1
公开(公告)日：2008-04-10
申请号：US11638703
申请日：2006-12-14
申请人： David Michael Bull , Shidhartha Das
发明人： David Michael Bull , Shidhartha Das
IPC分类号： G06F15/76
CPC分类号： G11C19/00
摘要： An integrated circuit 2 includes processing pipeline stages formed of an input register 8, processing circuit 10′, 10″ and an output register 12. The output register 12 employs speculative sampling and uses a subsequent speculation period during which any change in its input is detected and used to indicate a speculation error. In order to reduce the chances of a race condition giving rise to a false positive detection of a speculation error due to a too rapid signal propagation through the processing circuitry 10′, 10″, a transparent latch 14 is disposed at the approximate midpoint, measured in terms of propagation delay, within the processing circuitry 10′, 10″. This transparent latch 14 is non-transmissive during the speculation period of the output register 12 so as to prevent any new signal propagating from the input register 8 during the speculation period from reaching the output register 12.
摘要翻译： 集成电路2包括由输入寄存器8，处理电路10'，10“和输出寄存器12形成的处理流水线级。 输出寄存器12采用推测采样，并使用随后的推测周期，在此期间检测其输入中的任何变化并用于指示猜测误差。 为了减少由于通过处理电路10'，10“的信号传播太快导致的猜测误差的假阳性检测的竞争条件的机会，透明锁存器14设置在大致中点处， 在传播延迟方面测量，处理电路10'，10“内。 该透明锁存器14在输出寄存器12的推测周期期间是非透射的，以便在推测期间防止任何新的信号从输入寄存器8传播到达输出寄存器12。
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公开(公告)号：US09057761B2
公开(公告)日：2015-06-16
申请号：US13341547
申请日：2011-12-30
IPC分类号： G01R31/30
CPC分类号： G01R31/3004 , G01R31/30
摘要： An integrated circuit including a plurality of sensors configured to sense variations in supply voltage levels at points within the integrated circuit is disclosed. The plurality of sensors are distributed across the integrated circuit and have transistor devices such that process variations in the transistor devices within the sensors are such that a sensing result will have a random voltage offset that has a predetermined probability of lying within a pre-defined voltage offset range. The integrated circuit is configured to transmit results from multiple ones of the plurality of sensors to processing circuitry such that the variations in the supply voltage levels can be determined with a voltage offset range that is reduced compared to the pre-defined voltage offset range.
摘要翻译： 公开了一种集成电路，其包括被配置为感测集成电路内的点处的电源电压电平的变化的多个传感器。 多个传感器分布在整个集成电路上并且具有晶体管器件，使得传感器内的晶体管器件中的工艺变化使得感测结果将具有位于预定电压内的预定概率的随机电压偏移 偏移范围。 集成电路被配置为将结果从多个传感器中的多个传感器传送到处理电路，使得可以利用与预定电压偏移范围相比减小的电压偏移范围来确定电源电压电平的变化。
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公开(公告)号：US08471612B1
公开(公告)日：2013-06-25
申请号：US13545518
申请日：2012-07-10
申请人： David Michael Bull , Shidhartha Das
发明人： David Michael Bull , Shidhartha Das
IPC分类号： H03L7/06
CPC分类号： H03K3/0375
摘要： Signal value storage circuitry 2 includes transparent storage circuitry 4, transition detector circuitry 6 and error detecting circuitry 8. The transition detector circuitry serves to generate a detection pulse when a signal transition is detected at a signal node NS within the transparent storage circuitry. The error detecting circuitry generates an error indicating signal when this detection pulse overlaps in time with the non-transparent phase of a pulse clock signal controlling the signal valve storage circuitry for at least an overlap period TOV.
摘要翻译： 信号值存储电路2包括透明存储电路4，转换检测器电路6和错误检测电路8.当在透明存储电路内的信号节点NS处检测到信号转变时，转换检测器电路用于产生检测脉冲。 当该检测脉冲与控制信号阀存储电路的至少一个重叠周期TOV的脉冲时钟信号的非透明相位重叠时，误差检测电路产生错误指示信号。
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30.发明授权公开(公告)号：US07876634B2
公开(公告)日：2011-01-25
申请号：US12085901
申请日：2005-12-02
IPC分类号： G11C11/00
CPC分类号： G11C7/08 , G11C7/24 , G11C11/4125 , G11C29/12 , G11C29/12005 , G11C29/26
摘要： A data processing system comprising a memory array having a plurality of memory cells and read circuitry for reading a logic value stored in one of the plurality of memory cells. The read circuitry is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.
摘要翻译： 一种数据处理系统，包括具有多个存储器单元的存储器阵列和用于读取存储在多个存储器单元之一中的逻辑值的读取电路。 读取电路可操作地执行存储的逻辑值的两个基本上同时的读取。 提供电压控制器并且可操作以选择性地改变对存储器阵列的电源电压的电平。 提供检测电路，用于根据两个基本上同时的读取来检测当电源电压电平导致读取结果不可靠时。
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