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1.发明授权Data processing apparatus and method using monitoring circuitry to control operating parameters 有权数据处理装置和方法，使用监控电路来控制运行参数公开(公告)号：US08639987B2
公开(公告)日：2014-01-28
申请号：US12929848
申请日：2011-02-18
IPC分类号： G06F11/00
CPC分类号： G06F1/324 , G06F1/3296 , G06F11/076 , Y02D10/126 , Y02D10/172
摘要： A data processing apparatus and method are provided that use monitoring circuitry to control operating parameters of the data processing apparatus. The data processing apparatus has functional circuitry for performing data processing, the functional circuitry including error correction circuitry configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Tuneable monitoring circuitry monitors a characteristic indicative of changes in signal propagation delay within the functional circuitry and produces a control signal dependent on the monitored characteristic. In a continuous tuning mode operation, the tuneable monitoring circuitry modifies the dependency between the monitored characteristic and the control signal in dependence upon certain characteristics of the errors detected by the error correction circuitry. An operating parameter controller is then arranged, in the continuous mode of operation, to control one or more performance controlling operating parameters of the data processing apparatus in dependence upon the control signal. This enables efficient and robust control of those operating parameters in response to changes in environmental conditions.
摘要翻译： 提供一种使用监视电路来控制数据处理装置的操作参数的数据处理装置和方法。 所述数据处理装置具有用于执行数据处理的功能电路，所述功能电路包括错误校正电路，其被配置为检测功能电路的操作中的错误并修复这些操作中的错误。 可调节监控电路监视指示功能电路内的信号传播延迟的变化的特性，并产生取决于被监测特性的控制信号。 在连续调谐模式操作中，可调谐监视电路根据由纠错电路检测到的错误的某些特性来修改监视特性和控制信号之间的相关性。 然后，在连续操作模式下，设置操作参数控制器，以根据控制信号控制数据处理装置的一个或多个性能控制操作参数。 这可以响应于环境条件的变化而对这些操作参数进行有效和鲁棒的控制。
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公开(公告)号：US08639975B2
公开(公告)日：2014-01-28
申请号：US12926436
申请日：2010-11-17
IPC分类号： G06F11/00
CPC分类号： G06F11/0763 , H03M13/09
摘要： A data processing system 2 is used to perform processing operations to generate a result value. The processing circuitry which generates the result value has an error resistant portion 32 and an error prone portion 30. The probability of an error in operation of the error prone portion for a given set of operating parameters (clk, V) is greater than the probability of an error for that same set of operating parameters within the error resistant portion. Error detection circuitry 38 detects any errors arising in the error prone portion. Parameter control circuitry 40 responds to detected errors to adjust the set of operating parameters to maintain a non-zero error rate in the errors detected by the error detection circuitry. Errors within the one or more bits generated by the error prone portion are not corrected as the apparatus is tolerant to errors occurring within such bit values of the result value.
摘要翻译： 数据处理系统2用于执行处理操作以产生结果值。 产生结果值的处理电路具有抗错部分32和易错部分30.对于给定的一组操作参数（clk，V），错误倾向部分的操作错误的概率大于概率 在该抗误差部分内的相同的一组操作参数的误差。 错误检测电路38检测在易错部分中产生的任何错误。 参数控制电路40对检测到的错误进行响应，以调整该组操作参数，以便在错误检测电路检测到的错误中保持非零错误率。 由误差容易部分产生的一个或多个位内的错误不会被校正，因为该装置对结果值的这些比特值内发生的错误是容忍的。
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公开(公告)号：US09047184B2
公开(公告)日：2015-06-02
申请号：US13548236
申请日：2012-07-13
CPC分类号： G06F11/0721 , G06F11/0757 , G06F11/0793 , G06F11/1052
摘要： An integrated circuit includes processing pipeline circuitry comprising a plurality of pipeline stages separated by respective signal value storage circuitry. Timing detection circuitry to the processing pipeline circuitry serves to detect as timing violations any signal transitions arrive at the signal value storage circuits outside respective nominal timing windows. Error detection circuitry triggers an error correcting response if the timing detection circuitry indicates a predetermined pattern comprising a plurality of timing violations spread over a plurality of clock cycles of a clock signal controlling the processing pipeline circuitry. The predetermined pattern may be two consecutive timing violations.
摘要翻译： 集成电路包括处理流水线电路，其包括由相应的信号值存储电路隔开的多个流水线级。 处理流水线电路的定时检测电路用于检测作为定时违规，任何信号转换到达相应标称定时窗口外的信号值存储电路。 如果定时检测电路指示包括在控制处理流水线电路的时钟信号的多个时钟周期中扩展的多个定时违反的预定模式，则错误检测电路触发纠错响应。 预定模式可以是两个连续的定时违规。
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公开(公告)号：US20120124421A1
公开(公告)日：2012-05-17
申请号：US12926436
申请日：2010-11-17
IPC分类号： G06F11/07
CPC分类号： G06F11/0763 , H03M13/09
摘要： A data processing system 2 is used to perform processing operations to generate a result value. The processing circuitry which generates the result value has an error resistant portion 32 and an error prone portion 30. The probability of an error in operation of the error prone portion for a given set of operating parameters (clk, V) is greater than the probability of an error for that same set of operating parameters within the error resistant portion. Error detection circuitry 38 detects any errors arising in the error prone portion. Parameter control circuitry 40 responds to detected errors to adjust the set of operating parameters to maintain a non-zero error rate in the errors detected by the error detection circuitry. Errors within the one or more bits generated by the error prone portion are not corrected as the apparatus is tolerant to errors occurring within such bit values of the result value.
摘要翻译： 数据处理系统2用于执行处理操作以产生结果值。 产生结果值的处理电路具有抗错部分32和易错部分30.对于给定的一组操作参数（clk，V），错误倾向部分的操作错误的概率大于概率 在该抗误差部分内的相同的一组操作参数的误差。 错误检测电路38检测在易错部分中产生的任何错误。 参数控制电路40对检测到的错误进行响应，以调整该组操作参数，以便在错误检测电路检测到的错误中保持非零错误率。 由误差容易部分产生的一个或多个位内的错误不会被校正，因为该装置对结果值的这些比特值内发生的错误是容忍的。
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公开(公告)号：US20130169350A1
公开(公告)日：2013-07-04
申请号：US13341547
申请日：2011-12-30
IPC分类号： G11C5/14
CPC分类号： G01R31/3004 , G01R31/30
摘要： An integrated circuit comprising a plurality of sensors configured to sense variations in supply voltage levels at points within the integrated circuit is disclosed. The plurality of sensors are distributed across the integrated circuit and have transistor devices such that process variations in the transistor devices within the sensors are such that a sensing result will have a random voltage offset that has a predetermined probability of lying within a pre-defined voltage offset range. The integrated circuit is configured to transmit results from multiple ones of the plurality of sensors to processing circuitry such that the variations in the supply voltage levels can be determined with a voltage offset range that is reduced compared to the pre-defined voltage offset range.
摘要翻译： 公开了一种集成电路，其包括被配置为感测集成电路内的点处的电源电压电平的变化的多个传感器。 多个传感器分布在整个集成电路上并且具有晶体管器件，使得传感器内的晶体管器件中的工艺变化使得感测结果将具有位于预定电压内的预定概率的随机电压偏移 偏移范围。 集成电路被配置为将结果从多个传感器中的多个传感器传送到处理电路，使得可以利用与预定电压偏移范围相比减小的电压偏移范围来确定电源电压电平的变化。
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6.发明申请Data processing apparatus and method using monitoring circuitry to control operating parameters 有权数据处理装置和方法，使用监控电路来控制运行参数公开(公告)号：US20120216067A1
公开(公告)日：2012-08-23
申请号：US12929848
申请日：2011-02-18
IPC分类号： G06F11/07
CPC分类号： G06F1/324 , G06F1/3296 , G06F11/076 , Y02D10/126 , Y02D10/172
摘要： A data processing apparatus and method are provided that use monitoring circuitry to control operating parameters of the data processing apparatus. The data processing apparatus has functional circuitry for performing data processing, the functional circuitry including error correction circuitry configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Tuneable monitoring circuitry monitors a characteristic indicative of changes in signal propagation delay within the functional circuitry and produces a control signal dependent on the monitored characteristic. In a continuous tuning mode operation, the tuneable monitoring circuitry modifies the dependency between the monitored characteristic and the control signal in dependence upon certain characteristics of the errors detected by the error correction circuitry. An operating parameter controller is then arranged, in the continuous mode of operation, to control one or more performance controlling operating parameters of the data processing apparatus in dependence upon the control signal. This enables efficient and robust control of those operating parameters in response to changes in environmental conditions.
摘要翻译： 提供一种使用监视电路来控制数据处理装置的操作参数的数据处理装置和方法。 所述数据处理装置具有用于执行数据处理的功能电路，所述功能电路包括错误校正电路，其被配置为检测功能电路的操作中的错误并修复这些操作中的错误。 可调节监控电路监视指示功能电路内的信号传播延迟的变化的特性，并产生取决于被监测特性的控制信号。 在连续调谐模式操作中，可调谐监视电路根据由纠错电路检测到的错误的某些特性来修改监视特性和控制信号之间的相关性。 然后，在连续操作模式下，设置操作参数控制器，以根据控制信号控制数据处理装置的一个或多个性能控制操作参数。 这可以响应于环境条件的变化而对这些操作参数进行有效和鲁棒的控制。
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公开(公告)号：US09057761B2
公开(公告)日：2015-06-16
申请号：US13341547
申请日：2011-12-30
IPC分类号： G01R31/30
CPC分类号： G01R31/3004 , G01R31/30
摘要： An integrated circuit including a plurality of sensors configured to sense variations in supply voltage levels at points within the integrated circuit is disclosed. The plurality of sensors are distributed across the integrated circuit and have transistor devices such that process variations in the transistor devices within the sensors are such that a sensing result will have a random voltage offset that has a predetermined probability of lying within a pre-defined voltage offset range. The integrated circuit is configured to transmit results from multiple ones of the plurality of sensors to processing circuitry such that the variations in the supply voltage levels can be determined with a voltage offset range that is reduced compared to the pre-defined voltage offset range.
摘要翻译： 公开了一种集成电路，其包括被配置为感测集成电路内的点处的电源电压电平的变化的多个传感器。 多个传感器分布在整个集成电路上并且具有晶体管器件，使得传感器内的晶体管器件中的工艺变化使得感测结果将具有位于预定电压内的预定概率的随机电压偏移 偏移范围。 集成电路被配置为将结果从多个传感器中的多个传感器传送到处理电路，使得可以利用与预定电压偏移范围相比减小的电压偏移范围来确定电源电压电平的变化。
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公开(公告)号：US20140019815A1
公开(公告)日：2014-01-16
申请号：US13548236
申请日：2012-07-13
IPC分类号： G06F11/14
CPC分类号： G06F11/0721 , G06F11/0757 , G06F11/0793 , G06F11/1052
摘要： An integrated circuit 114 includes processing pipeline circuitry 40 comprising a plurality of pipeline stages 44, 46, 48 separated by respective signal value storage circuitry 48, 50, 52. Timing detection circuitry 54, 56, 58 coupled to the processing pipeline circuitry serves to detect as timing violations any signal transitions arrive at the signal value storage circuits outside respective nominal timing windows. Error detection circuitry 66 triggers an error correcting response if the timing detection circuitry indicates a predetermined pattern comprising a plurality of timing violations spread over a plurality of clock cycles of a clock signal CK controlling the processing pipeline circuitry. The predetermined pattern may be two consecutive timing violations.
摘要翻译： 集成电路114包括处理流水线电路40，其包括由相应的信号值存储电路48,50和52隔开的多个流水线段44,46,48。耦合到处理流水线电路的定时检测电路54,56,58用于检测 作为定时违反，任何信号转换都到达各个标称定时窗口之外的信号值存储电路。 如果定时检测电路指示包括在控制处理流水线电路的时钟信号CK的多个时钟周期内扩展的多个定时违反的预定模式，则错误检测电路66触发纠错响应。 预定模式可以是两个连续的定时违规。
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公开(公告)号：US20130002298A1
公开(公告)日：2013-01-03
申请号：US13067886
申请日：2011-07-01
CPC分类号： H03K3/0372 , H03K3/0375 , H03K5/1534
摘要： A D-type flip-flop 2 includes tristate inverter circuitry 4, 6 passing a processing signal through to storage circuitry 8 from where the processing signal passes via a transmission gate 10 to slave storage circuitry 12. A transition detector 16 is coupled to the input node nm of the storage circuitry 8 and serves to generate an error signal if a transition is detected upon that input node during an error detecting period. Other forms of this technique may provide clock gating circuitry.
摘要翻译： D型触发器2包括三态逆变器电路4,6将处理信号传递到存储电路8，处理信号从处理信号经由传输门10通过到从存储电路12.转换检测器16耦合到输入端 存储电路8的节点nm，并且用于在错误检测周期期间在该输入节点上检测到转换时产生误差信号。 该技术的其他形式可以提供时钟选通电路。
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公开(公告)号：US08327118B2
公开(公告)日：2012-12-04
申请号：US12458699
申请日：2009-07-21
申请人： David Michael Bull , Emre Ozer , Shidhartha Das
发明人： David Michael Bull , Emre Ozer , Shidhartha Das
CPC分类号： G06F9/3836 , G06F9/3861 , G06F9/3869 , G06F9/3891 , G06F11/004 , G06F11/1405
摘要： A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.
摘要翻译： 处理器2响应于程序指令流，以在调度电路6的控制下发出程序指令，以执行相应的执行单元24。 执行单元24可以包括用于检测在输出信号被锁存之后和在锁存输出信号之后的错误检测周期期间发生的输出信号的变化的错误检测电路32。 调度电路6被布置为在连续的处理周期中抑制对具有这种错误检测电路32的执行单元24的程序指令的发出。
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