公开(公告)号：US5574922A

公开(公告)日：1996-11-12

申请号：US261168

申请日：1994-06-17

申请人： David V. James

发明人： David V. James

IPC分类号： G06F9/46 ,  G06F15/00

CPC分类号： G06F9/526

摘要： A system and method for executing sequences of instructions which can be used to access a memory location in a locked fashion. The first instruction specifies an address and sets a lock register which disables interrupts until it is cleared. The second instruction specifies an address and clears the lock register. The second instruction is not executed if the lock register was already cleared and doesn't update memory if the cache line of the first address is no longer valid. If the second address is not cacheable, the instructions are off-loaded to the bus interface and the results of the update are used to update the processor state. The present invention allows locked memory updates and process synchronization without locking of arbitrary duration of the entire shared data structure. The calculation and update of the data structure may continue after a context switch. The present invention is compatible with a wide range of cache-coherence protocols.

摘要翻译： 一种用于执行指令序列的系统和方法，其可以用于以锁定方式访问存储器位置。 第一条指令指定一个地址，并设置一个禁止中断的锁定寄存器，直到它被清除。 第二条指令指定一个地址并清除锁定寄存器。 如果锁定寄存器已经被清除，并且如果第一个地址的高速缓存行不再有效，则不会更新存储器，否则不执行第二个指令。 如果第二个地址不可缓存，则指令将被卸载到总线接口，并且更新的结果用于更新处理器状态。 本发明允许锁定的存储器更新和处理同步而不锁定整个共享数据结构的任意持续时间。 在上下文切换之后，数据结构的计算和更新可以继续。 本发明与宽范围的高速缓存一致性协议兼容。

公开(公告)号：US5323426A

公开(公告)日：1994-06-21

申请号：US839973

申请日：1992-02-21

申请人： David V. James ,  Donald N. North ,  Glen D. Stone

发明人： David V. James ,  Donald N. North ,  Glen D. Stone

IPC分类号： G06F5/06 ,  H04J3/07 ,  H04L7/00

CPC分类号： G06F5/06 ,  H04J3/07

摘要： An elasticity buffer for use in a data transmission system having a transmitter and a receiver and utilizing a data transfer protocol that periodically supplies an elasticity element that can be deleted or replicated by the elasticity buffer to maintain the synchronous transfer of data elements. The elasticity buffer includes: a memory array and at least one flag per memory location operative to be set to a first or second state; a write controller operating at the transmitter clock for writing the data elements into the memory locations in a sequential order and setting the corresponding flags; a read controller operating at the receiver clock for reading the data elements from the memory locations in the sequential order; and a flag controller for reading the flags, determining if the transmitter clock is faster or slower than the receiver clock from the pattern of flags read from memory, communicating a delete signal to the read controller to delete an elastic symbol if the transmitter clock leads the receiver clock, and communicating a replicate signal to the read controller if the transmitter clock lags the receiver.

摘要翻译： 一种在具有发射机和接收机的数据传输系统中使用的弹性缓冲器，并且利用周期性地提供可由弹性缓冲器删除或复制的弹性元件以维持数据元素的同步传输的数据传输协议。 弹性缓冲器包括：存储器阵列和每个存储器位置的至少一个标志，其可操作地被设置为第一或第二状态; 在发射机时钟处操作的写控制器，用于以顺序的顺序将数据元素写入存储器位置并设置相应的标志; 在接收器时钟处操作的读取控制器，用于以顺序从存储器位置读取数据元素; 以及用于读取标志的标志控制器，根据从存储器读取的标志图案确定发送器时钟是否比接收器时钟更快或更慢，如果发送器时钟引导到传送器时钟，则将删除信号传送到读取控制器以删除弹性符号 接收机时钟，并且如果发射机时钟滞后于接收机，则将复制信号传送到读控制器。

公开(公告)号：US4779195A

公开(公告)日：1988-10-18

申请号：US750580

申请日：1985-06-28

申请人： David V. James

发明人： David V. James

IPC分类号： G06F9/48 ,  G06F13/24

CPC分类号： G06F13/24

摘要： Each processor in a system using the interrupt generation scheme has an external interrupt register (EIR) an input/output EIR (IO.sub.-- EIR) and an external interrupt mask register (EIM). When an I/O device wants to interrupt a first processor the I/O device writes a predetermined value to the first processor's IO.sub.-- EIR. When the predetermined value is written into the first processor's IO.sub.-- EIR, this causes a specified bit in the first processor's EIR to be set (or cleared depending upon system convention) and an interrupt to occur. The specified bit in the EIR indicates to the first processor either the I/O device which caused the interrupt, or a group of I/O devices which includes the I/O device which caused the interrupt. An I/O device can cause a bit in the EIR to be set, but only a processor can clear bits set in its EIR. The EIM is used by the processor to postpone taking action on an interrupt received from an I/O device. The processor takes action on an interrupt when an I/O device causes a bit to be set in the EIR, and a corresponding bit in the processor's EIM is set. If the corresponding bit in the EIM is not set, then the processor delays action on the interrupt until the corresponding bit in the EIM is set.

摘要翻译： 使用中断生成方案的系统中的每个处理器都有一个外部中断寄存器（EIR），一个输入/输出EIR（IO-EIR）和一个外部中断屏蔽寄存器（EIM）。 当I / O设备想要中断第一处理器时，I / O设备将预定值写入第一处理器的IO-EIR。 当预定值被写入到第一处理器的IO-EIR中时，这导致第一处理器的EIR中的指定位被设置（或者根据系统惯例被清除）并且发生中断。 EIR中的指定位向第一个处理器指示引起中断的I / O设备，还包括一组包含导致中断的I / O设备的I / O设备。 I / O设备可能导致EIR中的一个位被置位，但只有一个处理器可以清除其EIR中设置的位。 处理器使用EIM来延迟对从I / O设备接收到的中断采取措施。 当I / O设备导致在EIR中设置位时，处理器对中断采取动作，并且处理器的EIM中的相应位置1。 如果EIM中的相应位未设置，则处理器将延迟中断操作，直到设置了EIM中的相应位。

公开(公告)号：US07474586B1

公开(公告)日：2009-01-06

申请号：US12150146

申请日：2008-04-25

申请人： David V. James ,  Jagadeesan Rajamanickam

发明人： David V. James ,  Jagadeesan Rajamanickam

IPC分类号： G11C8/00

CPC分类号： G11C15/00

摘要： A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

摘要翻译： 公开了一种搜索引擎系统（100），其可以包括以级联配置布置的至少一个内容可寻址存储器（CAM）设备（102），其至少一个存储器设备（104），诸如静态随机存取存储器（SRAM） 。 CAM设备（102）和存储设备（104）可以通过点对点单向连接彼此连接。 由诸如网络处理单元（NPU）（110）的设备发布的命令数据可以流过从CAM设备（102）开始的所有设备，并且最终到达存储设备（104）。 存储器装置（104）可以将其自己的当前结果数据与流（例如另一RAM装置）中的先前装置的数据进行比较，并产生输出响应。

公开(公告)号：US06898201B1

公开(公告)日：2005-05-24

申请号：US10040166

申请日：2001-12-31

申请人： David V. James ,  William Rivard

发明人： David V. James ,  William Rivard

IPC分类号： H04L12/28 ,  H04L25/49

CPC分类号： H04L25/4908

摘要： A first set of signals is transformed into a second set of signals having a more stable set of current requirements. The more stable current requirements of the second set of signals are achieved by encoding the second set of signals with either an equal number, nearly an equal number, a constant number, or nearly a constant number of logic ones and logic zeros. A communication channel is provided for carrying the second set of signals from the first node to a second node.

摘要翻译： 第一组信号被转换成具有更稳定的电流要求集合的第二组信号。 第二组信号的更稳定的电流要求通过对具有相等数量，几乎相等的数量，常数或几乎恒定数量的逻辑1和逻辑零编码第二组信号来实现。 提供通信信道用于将第二组信号从第一节点传送到第二节点。

公开(公告)号：US06892273B1

公开(公告)日：2005-05-10

申请号：US10165560

申请日：2002-06-07

申请人： David V. James ,  Jagadecsan Raiamanickam

发明人： David V. James ,  Jagadecsan Raiamanickam

IPC分类号： G11C15/00 ,  G06F12/00

CPC分类号： G11C15/00

摘要： According to one embodiment, a method for storing content addressable memory (CAM) mask values may include storing mask values according to mask size in a mask register set (200). A mask register set (200) may include a number of locations arranged into regions (202, 204, 206 and 208). Each region (202, 204, 206 and 208) can store mask values of a different predetermined size.

摘要翻译： 根据一个实施例，一种用于存储内容寻址存储器（CAM）掩码值的方法可以包括根据掩码大小将掩码值存储在掩码寄存器集（200）中。 掩模寄存器组（200）可以包括布置在区域（202,204,206和208）中的多个位置。 每个区域（202,204,206和208）可以存储不同预定大小的掩模值。

公开(公告)号：US06584539B1

公开(公告)日：2003-06-24

申请号：US09531278

申请日：2000-03-18

申请人： David V. James ,  Bruce Fairman ,  Scott Smyers

发明人： David V. James ,  Bruce Fairman ,  Scott Smyers

IPC分类号： G06F1336

CPC分类号： H04L29/12254 ,  H04L12/1854 ,  H04L12/2803 ,  H04L12/2832 ,  H04L12/40065 ,  H04L12/40091 ,  H04L12/40117 ,  H04L12/4625 ,  H04L12/64 ,  H04L29/12009 ,  H04L29/12018 ,  H04L41/0896 ,  H04L41/12 ,  H04L45/00 ,  H04L45/48 ,  H04L47/12 ,  H04L61/00 ,  H04L61/10 ,  H04L61/2038 ,  H04L69/22 ,  H04L2012/2849

摘要： A method and system for distributing messages on a bus bridge interconnect are described. In one embodiment, the interconnect comprises a number of nodes, a bus bridge, and a number of buses. The method and system insure that the messages have been observed by each node. In one embodiment, a message is initiated at an initiating node. The message is forwarded to an adjacent neighbor node. The adjacent neighbor node processes and forwards the message to its adjacent neighbor node. The message is received at the initiating node in its original or modified form. In one embodiment, the message is removed from the interconnect once it is received by the initiating node. In an alternate embodiment, each node generates an appended message by one appending an extended unique identifier (EUI) to the message. Once the appended message is received at the initiating node, the appended message is saved.

摘要翻译： 描述了在总线桥互连上分发消息的方法和系统。 在一个实施例中，互连包括多个节点，总线桥和多个总线。 该方法和系统确保消息已被每个节点观察到。 在一个实施例中，在发起节点处发起消息。 该消息被转发到相邻邻居节点。 相邻邻居节点处理并将消息转发到其邻近邻居节点。 消息以其原始或修改形式在发起节点处接收。 在一个实施例中，一旦其由发起节点接收到消息就从互连中移除。 在替代实施例中，每个节点通过向消息附加扩展唯一标识符（EUI）来生成附加消息。 一旦在发起节点接收到附加的消息，就会保存附加的消息。

公开(公告)号：US06502158B1

公开(公告)日：2002-12-31

申请号：US09531084

申请日：2000-03-18

申请人： David V. James ,  Bruce Fairman

发明人： David V. James ,  Bruce Fairman

IPC分类号： G06F1300

CPC分类号： H04L61/2053 ,  H04L12/2803 ,  H04L12/40078 ,  H04L12/40091 ,  H04L12/40117 ,  H04L12/4625 ,  H04L12/6418 ,  H04L29/12009 ,  H04L29/12018 ,  H04L29/12254 ,  H04L29/12264 ,  H04L29/12273 ,  H04L29/12283 ,  H04L29/1232 ,  H04L29/12801 ,  H04L29/12839 ,  H04L41/0896 ,  H04L41/12 ,  H04L61/00 ,  H04L61/10 ,  H04L61/2038 ,  H04L61/2046 ,  H04L61/2061 ,  H04L61/2092 ,  H04L61/6004 ,  H04L61/6022 ,  H04L69/22 ,  H04L2012/2849

摘要： A system for allowing a node to be accessed through multiple address spaces. The system includes a virtual address memory providing a software settable bus identification address and a stable node identification address for each node in a net, a physical address memory providing a physically assigned node identification address for each node in a local bus, and a logical address memory providing a stable node identification address for each node in the local bus.

摘要翻译： 允许通过多个地址空间访问节点的系统。 该系统包括虚拟地址存储器，其为网络中的每个节点提供软件可设置的总线标识地址和稳定的节点标识地址，物理地址存储器为本地总线中的每个节点提供物理分配的节点标识地址，以及逻辑地址 内存为本地总线中的每个节点提供稳定的节点标识地址。

公开(公告)号：US06421745B1

公开(公告)日：2002-07-16

申请号：US09548050

申请日：2000-04-12

申请人： David V. James ,  Hisato Shima ,  Bruce Fairman

发明人： David V. James ,  Hisato Shima ,  Bruce Fairman

IPC分类号： G06F1314

CPC分类号： H04L47/266

摘要： Both small frames and large frames of data are transmitted from a producer device to a consumer device over an IEEE 1394 serial data bus. The small frames of data are preferably transmitted to a small frame buffer associated with a plug at the consumer device. Each transfer of a small frame generates an interrupt at the consumer device when the transfer is complete. For the transfer of large frames of data, the consumer device programs an array of page table entries into the plug control register of the producer device, prior to a transfer of a large frame of data. Each of the page table entries includes a starting address of a memory page at the consumer device to which data can be written. Together, these memory pages specified by the page table entries form a large frame buffer at the consumer device for receiving a large frame of data from the producer device. Preferably, the array of page table entries can be updated by the consumer device, as appropriate, between frame transfers. When transferring a large frame of data, the producer device begins writing to the first page specified in the first page table entry and continues in order, writing to the pages specified in the page table entries, until the entire frame has been transferred. When the entire large frame of data has been transferred, the producer device then updates the plug control register at the consumer device to notify the consumer device that the entire large frame has been transferred.

摘要翻译： 小帧和大帧数据都通过IEEE 1394串行数据总线从制作设备发送到消费者设备。 数据的较小帧优选地被发送到与消费者设备处的插头相关联的小帧缓冲器。 传输完成后，小帧的每次传送都会在消费者设备处产生中断。 为了传送大帧数据，消费者设备在传送大帧数据之前将页表条目数组编程到生成器设备的插头控制寄存器中。 每个页表条目包括消费者设备上可写入数据的存储器页面的起始地址。 由页表项指定的这些存储页一起在消费者设备处形成大的帧缓冲器，用于从生成器设备接收大帧数据。 优选地，可以由消费者设备适当地在帧传输之间更新页表条目的阵列。 当传送大帧数据时，生成器设备开始写入第一页表条目中指定的第一页，并按顺序继续，写入页表条目中指定的页面，直到整个帧被传送。 当整个大帧数据已被传送时，制作设备随后更新消费者设备处的插头控制寄存器，以通知消费者设备整个大帧已被传送。

公开(公告)号：US06321304B1

公开(公告)日：2001-11-20

申请号：US09235588

申请日：1999-01-22

申请人： David V. James

发明人： David V. James

IPC分类号： G06F1300

CPC分类号： G06F12/0824

摘要： In a mixed-protocol multiple-processor cache coherence computer system one processor may support read-only and read-write lists while another processor may support only read-write lists. Data copied to a cache is called a cache line while a copy of the same data remaining in memory is called a memory line. A memory line is stale when its associated cache line has been modified. The main memory of the system always points to the processor at the head of each list and includes indications of fresh and stale memory line states. The present invention deletes the head entry of a read-only cache-sharing list where the head entry supports read-only operations and the next-list entry supports only read-write operations. The head of the list informs the next-list entry that the next-list entry is about to become the head of the list. The main memory then repositions its head-pointer to the next-list entry and changes the memory state from fresh to stale. The head of the list then informs the next-list entry that the deletion is complete and the old head is thus deleted from the list.

摘要翻译： 在混合协议多处理器高速缓存一致性计算机系统中，一个处理器可以支持只读和读写列表，而另一处理器可以仅支持读写列表。 复制到高速缓存的数据称为高速缓存行，而存储器中剩余的相同数据的副本称为内存行。 当其相关联的高速缓存行已被修改时，内存条已过时。 系统的主要内存总是指向每个列表头部的处理器，并包括新鲜和过时的内存条状态的指示。 本发明删除只读高速缓存共享列表的头条目，其中头条目支持只读操作，下一列表条目仅支持读写操作。 列表的头部通知下一个列表条目下一个列表条目即将成为列表的头。 主内存然后将其头指针重新设置到下一列表条目，并将内存状态从新更改改为过期状态。 然后，列表的头部通知下一个列表条目删除完成，并且从头删除旧的头。