公开(公告)号：US06952017B2

公开(公告)日：2005-10-04

申请号：US10762955

申请日：2004-01-21

申请人： Jian Li ,  Xiao-Chun Mu ,  Mark Isenberger

发明人： Jian Li ,  Xiao-Chun Mu ,  Mark Isenberger

IPC分类号： H01L21/28 ,  H01L27/115 ,  H01L29/51 ,  H01L29/06

CPC分类号： H01L27/11502 ,  H01L21/28291 ,  H01L29/516

摘要： One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions.One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

摘要翻译： 本发明的一个实施方案涉及聚合物记忆装置及其制备方法。 聚合物存储器件可以包括根据各种实施例的满足表面工程需要的铁电聚合物存储器的复合层或单层。 铁电聚合物记忆结构可以包括结晶铁电聚合物层，例如单一和共聚物组合物。 该结构可以包括旋涂和/或Langmuir-Blodgett沉积的组合物。 本发明的一个实施方案涉及制备聚合物存储器件的实施方案的方法。 本发明的一个实施例涉及允许聚合物存储器件与各种现有主机接口的存储器系统。

公开(公告)号：US06858862B2

公开(公告)日：2005-02-22

申请号：US09896656

申请日：2001-06-29

申请人： Jian Li ,  Xiao-Chun Mu

发明人： Jian Li ,  Xiao-Chun Mu

IPC分类号： G11C11/22 ,  H01L27/115 ,  H01L29/06 ,  H01L29/12 ,  H01L33/00

CPC分类号： H01L27/11507 ,  B82Y10/00 ,  G11C11/22 ,  H01L27/11502

摘要： The invention relates to discrete, spaced-apart ferroelectric polymer memory device embodiments. The ferroelectric polymer memory device is fabricated by spin-on polymer processing and etching using photolithographic technology. The size of the discrete, spaced-apart ferroelectric polymer structures may be tied to a specific photolithography minimum feature dimension.The invention also relates to a process for making embodiments of a polymer memory device that includes discrete, spaced-apart ferroelectric polymer structures. The discrete, spaced-apart ferroelectric polymer structures may have a minimum feature that is tied to the current photolithography that may reduce the voltage and increase the switching speed.

摘要翻译： 本发明涉及离散的间隔开的铁电聚合物存储器件实施例。 通过使用光刻技术的旋涂聚合物处理和蚀刻来制造铁电聚合物存储器件。 离散的间隔开的铁电聚合物结构的尺寸可以与特定的光刻最小特征尺寸相关联。本发明还涉及一种用于制造聚合物存储器件的实施例的方法，该聚合物存储器件包括离散的间隔开的铁电聚合物结构。 离散的间隔开的铁电聚合物结构可以具有连接到当前光刻的最小特征，其可以降低电压并提高开关速度。

公开(公告)号：US06756620B2

公开(公告)日：2004-06-29

申请号：US09897174

申请日：2001-06-29

申请人： Jian Li ,  Xiao-Chun Mu ,  Mark Isenberger

发明人： Jian Li ,  Xiao-Chun Mu ,  Mark Isenberger

IPC分类号： H01L2144

CPC分类号： H01L27/11502 ,  H01L21/28291 ,  H01L29/516

摘要： One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions. One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

摘要翻译： 本发明的一个实施方案涉及聚合物记忆装置及其制备方法。 聚合物存储器件可以包括根据各种实施例的满足表面工程需要的铁电聚合物存储器的复合层或单层。 铁电聚合物记忆结构可以包括结晶铁电聚合物层，例如单一和共聚物组合物。 该结构可以包括旋转和/或Langmuir-Blodgett沉积的组合物。本发明的一个实施方案涉及制备聚合物存储器件的实施方案的方法。 本发明的一个实施例涉及允许聚合物存储器件与各种现有主机接口的存储器系统。

公开(公告)号：US06586836B1

公开(公告)日：2003-07-01

申请号：US09516652

申请日：2000-03-01

申请人： Qing Ma ,  Xiao-Chun Mu ,  Quat Vu ,  Steve Towle

发明人： Qing Ma ,  Xiao-Chun Mu ,  Quat Vu ,  Steve Towle

IPC分类号： H01L2348

CPC分类号： H01L24/19 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/96 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2224/92144 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

摘要： A method of fabricating microelectronic dice by providing or forming a first encapsulated die assembly and a second encapsulated die assembly. Each of the encapsulated die assemblies includes at least one microelectronic die disposed in an encapsulation material. Each of the encapsulated die assemblies has an active surface and a back surface. The encapsulated die assemblies are attached together in a back surface-to-back surface arrangement. Build-up layers are then formed on the active surfaces of the first and second encapsulated assemblies, preferably, simultaneously. Thereafter, the microelectronic dice are singulated, if required, and the microelectronic dice of the first encapsulated die assembly are separated from the microelectronic dice of the second encapsulated die assembly.

摘要翻译： 一种通过提供或形成第一封装模具组件和第二封装模具组件来制造微电子模具的方法。 每个封装的管芯组件包括设置在封装材料中的至少一个微电子管芯。 每个封装的模具组件具有活性表面和后表面。 封装的模头组件以后表面对背表面布置连接在一起。 然后，优选地，同时地，在第一和第二封装组件的活性表面上形成积层。 此后，如果需要，微电子骰子是单切的，并且第一封装模具组件的微电子骰子与第二封装模具组件的微电子骰子分开。

公开(公告)号：US5167760A

公开(公告)日：1992-12-01

申请号：US711361

申请日：1991-06-05

申请人： Xiao-Chun Mu ,  Jagir Multani

发明人： Xiao-Chun Mu ,  Jagir Multani

IPC分类号： H01L21/3213 ,  H01L21/768

CPC分类号： H01L21/7684 ,  H01L21/32136

摘要： An etchback process for etching a refractory metal layer formed on a semiconductor substrate with a greatly reduced micro-loading effect. The etch proceeds in three steps. The first step is a uniform etch which utilizes a gas chemistry of SF.sub.6, O.sub.2 and He and proceeds for a predetermined time to remove most of the metal layer. The second step is a very uniform etch which utilizes a gas chemistry of SF.sub.6, Cl.sub.2 and He and proceeds until the endpoint is detected. The endpoint is detected by measurement and integration of the 772 nm and 775 nm lines of Cl. The third step is a timed etch utilizing a gas chemistry of Cl.sub.2 and He which is used as both an overetch to ensure complete removal of the refractory metal film and as a selective etchant to remove an adhesion underlayer.

摘要翻译： 用于蚀刻形成在半导体衬底上的难熔金属层，具有大大降低的微负载效应的回蚀工艺。 蚀刻在三个步骤中进行。 第一步是使用SF6，O2和He的气体化学物质的均匀蚀刻，并且进行预定时间以去除大部分金属层。 第二步是使用SF6，Cl2和He的气体化学物质的非常均匀的蚀刻，并继续进行直到检测到端点。 通过测量和整合Cl的772nm和775nm线来检测终点。 第三步是利用Cl2和He的气体化学进行的定时蚀刻，其用作保护完全去除难熔金属膜的过滤材料，以及作为去除粘附底层的选择性蚀刻剂。