公开(公告)号：US07579237B2

公开(公告)日：2009-08-25

申请号：US11653362

申请日：2007-01-16

申请人： Sang-Kyoung Lee ,  Jin-Hong Kim ,  Dong-Hwan Kim ,  Won-Sik Shin ,  Woong Lee

发明人： Sang-Kyoung Lee ,  Jin-Hong Kim ,  Dong-Hwan Kim ,  Won-Sik Shin ,  Woong Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/4925

摘要： A method of manufacturing a nonvolatile memory device includes forming a plurality of device isolation regions in a semiconductor substrate, forming a tunneling insulation layer on the semiconductor substrate, forming a first preliminary polysilicon layer in communication with the tunneling insulation layer and the device isolation regions, forming a preliminary amorphous silicon layer on the first preliminary silicon layer, forming a second preliminary polysilicon layer on the preliminary amorphous silicon layer, and patterning the second preliminary polysilicon layer, the preliminary amorphous silicon layer, and the first preliminary polysilicon layer to form a floating gate layer.

摘要翻译： 一种制造非易失性存储器件的方法包括在半导体衬底中形成多个器件隔离区域，在半导体衬底上形成隧道绝缘层，形成与隧道绝缘层和器件隔离区域连通的第一初步多晶硅层， 在所述第一初步硅层上形成初步非晶硅层，在所述初步非晶硅层上形成第二初步多晶硅层，以及构图所述第二初步多晶硅层，所述初步非晶硅层和所述第一初步多晶硅层，以形成浮 门层

公开(公告)号：US07432745B2

公开(公告)日：2008-10-07

申请号：US11218384

申请日：2005-09-02

申请人： Jong-Tae Hwang ,  Yun-Kee Lee ,  Dong-Hwan Kim

发明人： Jong-Tae Hwang ,  Yun-Kee Lee ,  Dong-Hwan Kim

IPC分类号： H03K3/00

CPC分类号： H03K17/162 ,  H03K17/063 ,  H03K2217/0018

摘要： A high voltage gate driver circuit according to an embodiment of the present invention controls an operational range of an output signal of a level shifter to be appropriate for an operational range of a reshaper through a VIV converter. Even though the voltage range of the signal which is input from the high voltage gate driver circuit to the level shifter is different from the operational range of the reshaper, the input signal can always be recognized exactly regardless of the VTH voltage of the reshaper by controlling the operational range of the signal through the VIV converter. In addition, incorrect operation of the circuit can be prevented by erasing a common mode noise which is input with the input signal.

摘要翻译： 根据本发明实施例的高电压栅极驱动器电路通过VIV转换器控制电平移位器的输出信号的操作范围，以适合于整流器的工作范围。 即使从高电压栅极驱动电路向电平移位器输入的信号的电压范围与整流器的工作范围不同，也可以总是通过控制通过整流器的VTH电压来精确地识别输入信号 通过VIV转换器的信号的工作范围。 此外，通过擦除用输入信号输入的共模噪声可以防止电路的不正确的操作。

公开(公告)号：US07420431B2

公开(公告)日：2008-09-02

申请号：US11607357

申请日：2006-12-01

申请人： Jong-Tae Hwang ,  Dae-Ho Kim ,  Moon-Sang Jung ,  Dong-Hwan Kim

发明人： Jong-Tae Hwang ,  Dae-Ho Kim ,  Moon-Sang Jung ,  Dong-Hwan Kim

IPC分类号： H03K3/02

CPC分类号： H03K4/502

摘要： An RC oscillator integrated circuit includes: an active current mirror connected to an external resistor, for receiving a current signal corresponding to a voltage signal applied to the external resistor, performing 1/N-times division of the received current signal according to an input clock signal, and generating a 1/N-times current signal; an oscillation circuit for generating an output voltage corresponding to a charging- or discharging-operation of a capacitor via a current path formed by the active current mirror; a feedback switching circuit for controlling a charging- or discharging-path of the capacitor by a feedback of an output signal Vo of the oscillation circuit; and a divider for generating not only a first clock signal capable of driving the active current mirror according to the output signal of the oscillation circuit, but also a second output clock signal having a compensated mismatch of the active current mirror.

摘要翻译： RC振荡器集成电路包括：连接到外部电阻器的有源电流镜，用于接收与施加到外部电阻器的电压信号相对应的电流信号，根据输入时钟执行接收电流信号的1 / N次分频 信号，并产生1 / N倍电流信号; 振荡电路，用于经由由有源电流镜形成的电流路径产生对应于电容器的充电或放电操作的输出电压; 反馈开关电路，用于通过所述振荡电路的输出信号Vo的反馈来控制所述电容器的充电或放电路径; 以及用于根据振荡电路的输出信号产生能够驱动有源电流镜的第一时钟信号的分频器，还产生具有有源电流镜的补偿失配的第二输出时钟信号。

公开(公告)号：US07372528B2

公开(公告)日：2008-05-13

申请号：US10854850

申请日：2004-05-27

申请人： Jin Jeon ,  Jin-Suk Park ,  Dong-Hwan Kim ,  Kyo-Seop Choo ,  Yong-Ho Yang ,  Ji-Hye Moon ,  Won-Kyu Lee ,  Jun-Ho Song

发明人： Jin Jeon ,  Jin-Suk Park ,  Dong-Hwan Kim ,  Kyo-Seop Choo ,  Yong-Ho Yang ,  Ji-Hye Moon ,  Won-Kyu Lee ,  Jun-Ho Song

IPC分类号： G02F1/1333

CPC分类号： G02F1/136213 ,  G02F2001/136218

摘要： An array substrate includes a transparent substrate, pixel electrodes, switching devices, a data line, a gate line and a light blocking pattern. The light blocking pattern corresponding to a storage electrode is disposed on the transparent substrate, and the light blocking pattern blocks a light leaked from a space between the pixel electrodes. The pixel electrodes are spaced apart from the light blocking pattern by a first distance. The data line is spaced apart from the light blocking pattern by a second distance, and the data line is disposed under a region between the pixel electrodes. The data line is electrically connected to the source electrode, and the data line has a first width. The gate line is electrically connected to the gate electrode to turn on/off the switching devices. Therefore, a black matrix is not required, thereby enhancing an aperture ratio.

摘要翻译： 阵列基板包括透明基板，像素电极，开关元件，数据线，栅极线和遮光图案。 对应于存储电极的遮光图案设置在透明基板上，并且遮光图案阻挡从像素电极之间的空间泄漏的光。 像素电极与遮光图案间隔开第一距离。 数据线与遮光图案隔开第二距离，数据线设置在像素电极之间的区域之下。 数据线与源电极电连接，数据线具有第一宽度。 栅极线电连接到栅电极，以便开/关开关器件。 因此，不需要黑矩阵，从而提高孔径比。

公开(公告)号：US07323825B2

公开(公告)日：2008-01-29

申请号：US11607358

申请日：2006-12-01

申请人： Jong-Tae Hwang ,  Dae-Ho Kim ,  Moon-Sang Jung ,  Dong-Hwan Kim

发明人： Jong-Tae Hwang ,  Dae-Ho Kim ,  Moon-Sang Jung ,  Dong-Hwan Kim

IPC分类号： H05B37/02

CPC分类号： H05B41/2985 ,  H05B41/2981 ,  H05B41/2986

摘要： A ballast integrated circuit (IC) for driving a first switching element and a second switching element includes: a variable gain amplifier (VGA) connected to a first input terminal connected to a resistor, for generating an output current signal according to a resistance value of the resistor and a gain control signal; a preheating/ignition controller connected to a second input terminal connected to a capacitor, for generating an output current signal and an output voltage signal acting as the gain control signal according to a voltage of the second input terminal; an active zero-voltage controller for generating a hard-switching current signal and an active zero-voltage switching current signal, such that it adjusts the voltage of the second input terminal according to switching states of the first switching element and the second switching element; an oscillator for generating an oscillation signal upon receiving the output current signal from the variable gain amplifier (VGA); and a dead-time controller for receiving the voltage signal of the second input terminal and an output signal of the oscillator, adjusting a dead time using the received signals, and at the same time generating driving signals of the first and second switching elements.

摘要翻译： 用于驱动第一开关元件和第二开关元件的镇流器集成电路（IC）包括：连接到连接到电阻器的第一输入端子的可变增益放大器（VGA），用于根据电阻值的电阻值产生输出电流信号 电阻和增益控制信号; 连接到连接到电容器的第二输入端子的预热/点火控制器，用于根据第二输入端子的电压产生作为增益控制信号的输出电流信号和输出电压信号; 用于产生硬切换电流信号和有效零电压开关电流信号的有源零电压控制器，使得其根据第一开关元件和第二开关元件的开关状态来调节第二输入端子的电压; 用于在从可变增益放大器（VGA）接收输出电流信号时产生振荡信号的振荡器; 以及用于接收第二输入端子的电压信号和振荡器的输出信号的死区时间控制器，使用接收信号调整死区时间，同时产生第一和第二开关元件的驱动信号。

公开(公告)号：US07254064B2

公开(公告)日：2007-08-07

申请号：US11356620

申请日：2006-02-17

申请人： Dong-Hwan Kim ,  Yeong-Taek Lee

发明人： Dong-Hwan Kim ,  Yeong-Taek Lee

IPC分类号： G11C7/10

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5642

摘要： There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations.

摘要翻译： 提供了一种具有多电平单元的闪存器件及其读取和编程方法。 具有多电平单元的闪速存储器件包括存储单元阵列，用于对位线进行预充电的单元，用于向位线提供电压的位线电压供应电路，以及每个都执行与位线不同的功能的第一至第三锁存电路 彼此。 读取和编程方法由LSB和MSB读取和编程操作执行。 通过读取LSB两次并通过读取MSB一次来实现存储器件中的读取方法。 通过编程LSB一次并编程MSB一次来实现编程方法。 具有多级数据的数据可以通过两次编程操作被编程到存储器单元中。

公开(公告)号：US20070146087A1

公开(公告)日：2007-06-28

申请号：US11607357

申请日：2006-12-01

申请人： Jong-Tae Hwang ,  Dae-Ho Kim ,  Moon-Sang Jung ,  Dong-Hwan Kim

发明人： Jong-Tae Hwang ,  Dae-Ho Kim ,  Moon-Sang Jung ,  Dong-Hwan Kim

IPC分类号： H03K3/26

CPC分类号： H03K4/502

摘要： An RC oscillator integrated circuit includes: an active current mirror connected to an external resistor, for receiving a current signal corresponding to a voltage signal applied to the external resistor, performing 1/N-times division of the received current signal according to an input clock signal, and generating a 1/N-times current signal; an oscillation circuit for generating an output voltage corresponding to a charging- or discharging-operation of a capacitor via a current path formed by the active current mirror; a feedback switching circuit for controlling a charging- or discharging-path of the capacitor by a feedback of an output signal Vo of the oscillation circuit; and a divider for generating not only a first clock signal capable of driving the active current mirror according to the output signal of the oscillation circuit, but also a second output clock signal having a compensated mismatch of the active current mirror.

摘要翻译： RC振荡器集成电路包括：连接到外部电阻器的有源电流镜，用于接收与施加到外部电阻器的电压信号相对应的电流信号，根据输入时钟执行接收电流信号的1 / N次分频 信号，并产生1 / N倍电流信号; 振荡电路，用于经由由有源电流镜形成的电流路径产生对应于电容器的充电或放电操作的输出电压; 反馈开关电路，用于通过所述振荡电路的输出信号Vo的反馈来控制所述电容器的充电或放电路径; 以及用于根据振荡电路的输出信号产生能够驱动有源电流镜的第一时钟信号的分频器，还产生具有有源电流镜的补偿失配的第二输出时钟信号。

公开(公告)号：US07062390B2

公开(公告)日：2006-06-13

申请号：US10612080

申请日：2003-07-01

申请人： Dong-Hwan Kim ,  Sang-Hyo Ryu ,  Hyung-Song Lee

发明人： Dong-Hwan Kim ,  Sang-Hyo Ryu ,  Hyung-Song Lee

IPC分类号： G01N27/416

CPC分类号： G01R31/3651 ,  G01R31/3662

摘要： The present invention relates to a method for evaluating an initial capacity of secondary batteries and, more specifically, to a method for evaluating an initial capacity of secondary batteries that involves mathematical operation of specific internal resistance components obtained from an equivalent circuit model of an impedance spectrum measured for a short time period instead of using direct discharge characteristics, thereby allowing selection of batteries having a different initial discharge characteristic.

摘要翻译： 本发明涉及一种用于评估二次电池的初始容量的方法，更具体地，涉及一种用于评估二次电池的初始容量的方法，所述二次电池的初始容量包括从阻抗谱的等效电路模型获得的特定内部电阻分量的数学运算 测量短时间段而不是使用直接放电特性，从而允许选择具有不同初始放电特性的电池。

公开(公告)号：US20060110949A1

公开(公告)日：2006-05-25

申请号：US11265387

申请日：2005-11-02

申请人： Ahn-Ho Jee ,  Kun-Bin Lee ,  Dong-Hwan Kim ,  Hyeong-Cheol Ahn

发明人： Ahn-Ho Jee ,  Kun-Bin Lee ,  Dong-Hwan Kim ,  Hyeong-Cheol Ahn

IPC分类号： H01R12/00

CPC分类号： G02F1/133608 ,  G02F1/133308 ,  G02F2001/133314 ,  H01R13/2442 ,  H01R13/6471 ,  H01R13/6581 ,  H01R13/6585 ,  H05K9/0067

摘要： A receiving container for a display device includes a bottom plate, a sidewall and a grounding unit. The sidewall is extended from the bottom plate to define a receiving space. The grounding unit is integrally formed with the bottom plate. The grounding unit includes a grounding member that grounds a circuit board received in the receiving space. The circuit board includes a grounding electrode and the grounding member corresponds to the grounding electrode. The grounding member is formed on a rear surface of the bottom plate. The grounding member may include a protrusion or a projected portion having an elastic structure.

摘要翻译： 用于显示装置的接收容器包括底板，侧壁和接地单元。 侧壁从底板延伸以限定接收空间。 接地单元与底板一体形成。 接地单元包括使接收在接收空间中的电路板接地的接地构件。 电路板包括接地电极，接地部件对应于接地电极。 接地构件形成在底板的后表面上。 接地构件可以包括具有弹性结构的突起或突出部分。

公开(公告)号：US20050081959A1

公开(公告)日：2005-04-21

申请号：US10734544

申请日：2003-12-12

申请人： Andrew Kim ,  Seok Namkung ,  Dong-Hwan Kim

发明人： Andrew Kim ,  Seok Namkung ,  Dong-Hwan Kim

IPC分类号： H01F1/057 ,  H01F1/09 ,  H01F1/06

CPC分类号： H01F1/09 ,  H01F1/0573

摘要： Disclosed is a method of preparing a micro-structured powder for bonded magnets having high coercivity, which is advantageous in terms of low preparation costs by recycling magnet scraps, simplified mass production, minimal environmental contamination by such a recycling process, and the preparation of stable anisotropic powders having high coercivity. Further, a magnet powder prepared by the above method is provided. The current method is characterized in that R—Fe—B type anisotropic sintered magnets or scraps thereof are crushed to prepare 50-500 μm sized magnet powders, which are then mixed with 1-10 wt % of rare earth fluoride (RF3) powders and thermally treated at high temperatures (500-1100° C.) in a vacuum or an inert gas, to cause the change of matrix-near surface and grain boundary of the powders. Thus obtained powders include a matrix phase having R2Fe14B crystal structure, a R-rich grain boundary phase containing rare earth fluoride, and other phases, in which the matrix phase has an average grain size of 1-20 μm, and the powders have an average size of 50-500 μm with superior magnetic characteristics of (BH)max≧20 MGOe and iHc≧5 kOe.

摘要翻译： 公开了一种制备具有高矫顽力的粘结磁体的微结构粉末的方法，其通过回收磁体废料，简化的批量生产，通过这种再循环过程的最小环境污染而制备成本低，并且制备稳定的 具有高矫顽力的各向异性粉末。 此外，提供通过上述方法制备的磁铁粉末。 目前的方法的特征在于将R-Fe-B型各向异性烧结磁体或其废料压碎以制备50-500毫米尺寸的磁体粉末，然后与1-10重量％的稀土氟化物（RF < 3）粉末，并在真空或惰性气体中在高温（500-1100℃）下进行热处理，导致粉末的基质 - 近表面和晶界的变化。 由此获得的粉末包括具有R 2 Fe 14 B晶体结构的基质相，含有稀土氟化物的富R晶界相和其它相，其中基质 相的平均粒径为1-20μm，粉末的平均粒径为50-500μm，具有优异的（BH）max> = 20MGOe和iHc> 5kOe的磁特性。