公开(公告)号：US07821315B2

公开(公告)日：2010-10-26

申请号：US11962689

申请日：2007-12-21

Applicant: Frederic Bossu ,  Anthony Francis Segoria

Inventor： Frederic Bossu ,  Anthony Francis Segoria

IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: Techniques are disclosed for adjusting and programming the duty cycle of a signal generated by a circuit. In an embodiment, parallel transistors are coupled between a NAND gate and a supply voltage. Selectively enabling the parallel transistors adjusts the switching point of the NAND gate, thereby allowing control of the pulse width of the output signal. In an alternative embodiment, the size of the PMOS versus the NMOS transistors in the NAND gate is selectively varied to achieve the same effect. Further disclosed are applications of the techniques to calibrating the receiver to minimize measured second-order inter-modulation products and/or residual sideband.

Abstract translation: 公开了用于调整和编程由电路产生的信号的占空比的技术。 在一个实施例中，并联晶体管耦合在NAND门和电源电压之间。 选择性地使并行晶体管调节NAND门的切换点，从而允许控制输出信号的脉冲宽度。 在替代实施例中，PMOS与NMOS门中的NMOS晶体管的尺寸有选择地变化以达到相同的效果。 进一步公开的是用于校准接收机以最小化测量的二阶互调产物和/或残留边带的技术的应用。

公开(公告)号：US20090111414A1

公开(公告)日：2009-04-30

申请号：US11955201

申请日：2007-12-12

Applicant: Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

Inventor： Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

IPC: H04B1/16

CPC classification number: H03D7/1441 ,  H03D7/165 ,  H03D7/166 ,  H03D2200/0084 ,  H03D2200/009

Abstract: Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an embodiment, LO buffer and/or mixer size may be increased when a receiver operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver operates in a low gain mode. In an embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific embodiments of LO buffers and mixers having adjustable size are disclosed.

Abstract translation: 公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。 在一个实施例中，当接收机以高增益模式工作时，可以增加LO缓冲器和/或混频器的大小，而当接收器以低增益模式工作时，可以减小LO缓冲器和/或混频器的大小。 在一个实施例中，LO缓冲器和混合器尺寸在锁定步骤中增加和减小。 公开了具有可调节尺寸的LO缓冲器和混合器的具体实施例的电路拓扑和控制方案。

公开(公告)号：US20050195034A1

公开(公告)日：2005-09-08

申请号：US11025848

申请日：2004-12-29

Applicant: Jean-Charles Grasset ,  Frederic Bossu

Inventor： Jean-Charles Grasset ,  Frederic Bossu

IPC: H03G1/04 ,  H03G7/06 ,  H03F3/45

CPC classification number: H03G1/04 ,  H03G7/06

Abstract: Attenuation cell comprising first and second differential pairs of bipolar transistors. A gain control device applies a voltage VA-VB between the bases of both differential pairs and comprises a set of three diodes in which a current IA, a current IB and the sum IA+IB of both preceding currents flow, respectively. The two diodes seeing current IB and IA+IB generate a voltage, respectively VB and VC, and the difference between these two voltages is used to generate a value Iz used in a control loop. A desired value Vct is transformed into information Ix, then into information Iy proportional to absolute temperature T, and an error amplifier uses information Iy-Iz and generates currents IA and IB by minimizing this difference.

Abstract translation: 衰减单元包括第一和第二差分双极晶体管对。 增益控制装置在两个差分对的基极之间施加电压VA-VB，并且包括一组三个二极管，其中电流IA，电流IB和前两个电流的和IA + IB分别流动。 看到电流IB和IA + IB的两个二极管分别产生VB和VC的电压，并且使用这两个电压之间的差来产生在控制回路中使用的值Iz。 期望值Vct被转换成信息Ix，然后转换成与绝对温度T成比例的信息Iy，误差放大器使用信息Iy-Iz，并通过最小化该差来产生电流IA和IB。

公开(公告)号：US09300420B2

公开(公告)日：2016-03-29

申请号：US13609532

申请日：2012-09-11

Applicant: Li-Chung Chang ,  Prasad Srinivasa Siva Gudem ,  Frederic Bossu ,  Christian Holenstein

Inventor： Li-Chung Chang ,  Prasad Srinivasa Siva Gudem ,  Frederic Bossu ,  Christian Holenstein

IPC: H04J3/02 ,  H04J3/00 ,  H03F3/72 ,  H04B1/00

CPC classification number: H04J3/00 ,  H03F3/72 ,  H04B1/0064 ,  H04B1/0071

Abstract: A receiver architecture for carrier aggregation is disclosed. In an exemplary design, an apparatus (e.g., a wireless device, a circuit module, etc.) includes a plurality of low noise amplifiers (LNAs), a plurality of switches, and at least one downconverter. The LNAs receive and amplify at least one input radio frequency (RF) signal and provide at least one amplified RF signal. The switches are coupled to the outputs of the plurality of LNAs. The at least one downconverter is coupled to the plurality of switches, downconverts the at least one amplified RF signal, and provides at least one downconverted signal. The switches reduce the number of downconverters needed to support reception of transmissions on multiple sets of carriers via multiple receive antennas. The LNAs and the switches may be implemented on at least one front-end module or a back-end module. The downconverter(s) are implemented on the back-end module.

Abstract translation: 公开了用于载波聚合的接收机架构。 在示例性设计中，装置（例如，无线装置，电路模块等）包括多个低噪声放大器（LNA），多个开关和至少一个下变频器。 LNA接收和放大至少一个输入射频（RF）信号并提供至少一个放大的RF信号。 开关耦合到多个LNA的输出端。 所述至少一个下变频器耦合到所述多个开关，对所述至少一个放大的RF信号进行下变频，并提供至少一个下变频信号。 交换机减少了通过多个接收天线支持在多组载波上接收传输所需的下变频器的数量。 LNA和交换机可以在至少一个前端模块或后端模块上实现。 下变频器在后端模块上实现。

公开(公告)号：US09287886B2

公开(公告)日：2016-03-15

申请号：US12366441

申请日：2009-02-05

Applicant: Steven C. Ciccarelli ,  Frederic Bossu ,  Vladimir Aparin ,  Kevin H. Wang

Inventor： Steven C. Ciccarelli ,  Frederic Bossu ,  Vladimir Aparin ,  Kevin H. Wang

IPC: H04B1/40 ,  H03L7/197

CPC classification number: H03L7/1974

Abstract: Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.

Abstract translation: 在接收机内，提供给分数N锁相环（PLL）的比较参考时钟信号的频率被动态地改变，使得具有已知干扰的参考杂波（例如，传输泄漏）的不期望的相互混合被最小化。 当发射信道在频带内变化时，并且随着发射泄漏频率的变化，电路改变比较参考时钟信号的频率，使得PLL产生的参考杂波频率移动，使得它们不与发射机泄漏相互混合 以不良的方式。 在第二方面，PLL可以作为整数N个PLL或分数N PLL来操作。 在低总接收功率情况下，PLL作为整数N PLL进行操作，以减少接收机对分数N个杂散的敏感性。 在第三方面，使用干扰检测信息来确定比较参考时钟信号频率。

公开(公告)号：US20140072001A1

公开(公告)日：2014-03-13

申请号：US13609532

申请日：2012-09-11

Applicant: Li-Chung Chang ,  Prasad Srinivasa Siva Gudem ,  Frederic Bossu ,  Christian Holenstein

Inventor： Li-Chung Chang ,  Prasad Srinivasa Siva Gudem ,  Frederic Bossu ,  Christian Holenstein

IPC: H04J3/00

CPC classification number: H04J3/00 ,  H03F3/72 ,  H04B1/0064 ,  H04B1/0071

Abstract: A receiver architecture for carrier aggregation is disclosed. In an exemplary design, an apparatus (e.g., a wireless device, a circuit module, etc.) includes a plurality of low noise amplifiers (LNAs), a plurality of switches, and at least one downconverter. The LNAs receive and amplify at least one input radio frequency (RF) signal and provide at least one amplified RF signal. The switches are coupled to the outputs of the plurality of LNAs. The at least one downconverter is coupled to the plurality of switches, downconverts the at least one amplified RF signal, and provides at least one downconverted signal. The switches reduce the number of downconverters needed to support reception of transmissions on multiple sets of carriers via multiple receive antennas. The LNAs and the switches may be implemented on at least one front-end module or a back-end module. The downconverter(s) are implemented on the back-end module.

Abstract translation: 公开了用于载波聚合的接收机架构。 在示例性设计中，装置（例如，无线装置，电路模块等）包括多个低噪声放大器（LNA），多个开关和至少一个下变频器。 LNA接收和放大至少一个输入射频（RF）信号并提供至少一个放大的RF信号。 开关耦合到多个LNA的输出端。 所述至少一个下变频器耦合到所述多个开关，对所述至少一个放大的RF信号进行下变频，并提供至少一个下变频信号。 交换机减少了通过多个接收天线支持在多组载波上接收传输所需的下变频器的数量。 LNA和交换机可以在至少一个前端模块或后端模块上实现。 下变频器在后端模块上实现。

公开(公告)号：US08019310B2

公开(公告)日：2011-09-13

申请号：US11955201

申请日：2007-12-12

Applicant: Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

Inventor： Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

IPC: H04B1/26 ,  H04B7/00 ,  H04B15/00

CPC classification number: H03D7/1441 ,  H03D7/165 ,  H03D7/166 ,  H03D2200/0084 ,  H03D2200/009

Abstract: Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an embodiment, LO buffer and/or mixer size may be increased when a receiver operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver operates in a low gain mode. In an embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific embodiments of LO buffers and mixers having adjustable size are disclosed.

Abstract translation: 公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。 在一个实施例中，当接收机以高增益模式工作时，可以增加LO缓冲器和/或混频器的大小，而当接收器以低增益模式工作时，可以减小LO缓冲器和/或混频器的大小。 在一个实施例中，LO缓冲器和混合器尺寸在锁定步骤中增加和减小。 公开了具有可调节尺寸的LO缓冲器和混合器的具体实施例的电路拓扑和控制方案。

公开(公告)号：US20090121763A1

公开(公告)日：2009-05-14

申请号：US11962689

申请日：2007-12-21

Applicant: Frederic Bossu ,  Anthony Francis Segoria

Inventor： Frederic Bossu ,  Anthony Francis Segoria

IPC: H03K3/017

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: Techniques are disclosed for adjusting and programming the duty cycle of a signal generated by a circuit. In an embodiment, parallel transistors are coupled between a NAND gate and a supply voltage. Selectively enabling the parallel transistors adjusts the switching point of the NAND gate, thereby allowing control of the pulse width of the output signal. In an alternative embodiment, the size of the PMOS versus the NMOS transitors in the NAND gate is selectively varied to achieve the same effect. Further disclosed are applications of the techniques to calibrating the receiver to minimize measured second-order inter-modulation products and/or residual sideband.

Abstract translation: 公开了用于调整和编程由电路产生的信号的占空比的技术。 在一个实施例中，并联晶体管耦合在NAND门和电源电压之间。 选择性地使并行晶体管调节NAND门的切换点，从而允许控制输出信号的脉冲宽度。 在替代实施例中，PMOS与NMOS栅极中的NMOS晶体管的尺寸有选择地变化以达到相同的效果。 进一步公开的是用于校准接收机以最小化测量的二阶互调产物和/或残留边带的技术的应用。

公开(公告)号：US20090075620A1

公开(公告)日：2009-03-19

申请号：US12209164

申请日：2008-09-11

Applicant: Sankaran Aniruddhan ,  Chiewcharn Narathong ,  Sriramgopal Sridhara ,  Ravi Sridhara ,  Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

Inventor： Sankaran Aniruddhan ,  Chiewcharn Narathong ,  Sriramgopal Sridhara ,  Ravi Sridhara ,  Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

IPC: H04B1/26

CPC classification number: H03D7/166 ,  H03D7/1441 ,  H03D7/1483 ,  H03D7/165 ,  H03D2200/0025 ,  H03G3/3052

Abstract: Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.

Abstract translation: 公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。 在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。 在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。 公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。

公开(公告)号：US08878613B2

公开(公告)日：2014-11-04

申请号：US13316621

申请日：2011-12-12

Applicant: Kevin H. Wang ,  Saru Palakurty ,  Frederic Bossu

Inventor： Kevin H. Wang ,  Saru Palakurty ,  Frederic Bossu

IPC: H03L7/093

CPC classification number: G04F10/005

Abstract: A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.

Abstract translation: 描述具有小于一个逆变器延迟的精细分辨率的时间 - 数字转换器（TDC）。 在示例性设计中，TDC包括第一和第二延迟路径，延迟单元和相位计算单元。 第一延迟路径接收第一输入信号和第一参考信号并提供第一输出。 第二延迟路径接收第二输入信号和第二参考信号并提供第二输出。 延迟单元相对于第一输入信号延迟第二输入信号或相对于第一参考信号延迟第二参考信号，例如延迟半个逆变器延迟。 相位计算单元接收第一和第二输出，并且在输入信号和参考信号之间提供相位差。 可以执行校准以获得第一和第二延迟路径的精确定时。