公开(公告)号：US5802330A

公开(公告)日：1998-09-01

申请号：US644405

申请日：1996-05-01

申请人： Drew J. Dutton

发明人： Drew J. Dutton

IPC分类号： G06F13/364 ,  G06F13/18

CPC分类号： G06F13/364

摘要： A computer system includes a bus arbiter for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of programmable registers are provided to receive configuration information for controlling the relative priority given to each of the bus masters when bus request contention occurs. One or more of the bus masters includes an arbitration feedback control circuit and feedback register for generating and storing a value to indicate whether the latency in obtaining the bus during a previous bus request phase was generous, was acceptable, or was longer than desired (i.e., the latency requirement for the device was either violated or the latency in obtaining the bus reached a near-critical point). If the value in the feedback register of a particular peripheral indicates the master desires faster access to the bus, an arbitration control unit of the bus arbiter increases a level of arbitration priority given to that master for future bus requests. Similarly, if the value in the feedback register of a peripheral indicates the master received ownership of the bus during a previous bus request phase with ample time, the arbitration control unit may decrease a level of arbitration priority given to the device.

摘要翻译： 计算机系统包括总线仲裁器，用于控制总线的所有权，多个实时和非实时资源都耦合到总线上。 总线仲裁器包括用于检测多个总线主机的总线请求信号的请求检测单元，以及用于产生相应的授权信号的授权发生器，用于指示总线的所有权授权。 提供一组可编程寄存器以接收配置信息，用于当发生总线请求争用时控制给予每个总线主机的相对优先级。 一个或多个总线主机包括仲裁反馈控制电路和反馈寄存器，用于产生和存储一个值，以指示在先前的总线请求阶段期间获得总线的延迟是否是大的，是可接受的，或者比期望的长（即 ，设备的等待时间要求被侵犯或获得总线的延迟达到了临近点）。 如果特定外设的反馈寄存器中的值指示主机希望更快地访问总线，则总线仲裁器的仲裁控制单元增加给予该主机的未来总线请求的仲裁优先级。 类似地，如果外设的反馈寄存器中的值指示主机在具有足够时间的先前总线请求阶段期间接收到总线的所有权，则仲裁控制单元可以降低给予该设备的仲裁优先级。

公开(公告)号：US20140251517A1

公开(公告)日：2014-09-11

申请号：US14281260

申请日：2014-05-19

申请人： Drew J. Dutton

发明人： Drew J. Dutton

IPC分类号： B60B9/04

CPC分类号： B60B9/04 ,  B60B9/26

摘要： An interlocking, compressible spoke wheel system having a ring of paired spokes. The locking of left and right spokes into pairs provides improved tire displacement under loads. The left and right half wheels formed by sets of left spokes and right spokes. enable a novel mounting system for the wheel rim or tire to attach to the spoke system.

摘要翻译： 具有成对辐条环的互锁的可压缩辐条轮系统。 将左右轮辐锁定成对可以提供改善的载荷下的轮胎位移。 由左侧辐条和右辐条组成的左右半轮。 使得轮缘或轮胎的新型安装系统能够附接到辐条系统。

公开(公告)号：US08757228B2

公开(公告)日：2014-06-24

申请号：US13074394

申请日：2011-03-29

申请人： Drew J. Dutton

发明人： Drew J. Dutton

IPC分类号： B60B9/02

CPC分类号： B60B9/04 ,  B60B9/26

摘要： An interlocking, compressible spoke wheel system having a ring of paired spokes. The locking of left and right spokes into pairs provides improved tire displacement under loads. The left and right half wheels formed by sets of left spokes and right spokes. enable a novel mounting system for the wheel rim or tire to attach to the spoke system.

摘要翻译： 具有成对辐条环的互锁的可压缩辐条轮系统。 将左右轮辐锁定成对可以提供改善的载荷下的轮胎位移。 由左侧辐条和右辐条组成的左右半轮。 使得轮缘或轮胎的新型安装系统能够附接到辐条系统。

公开(公告)号：US08149000B2

公开(公告)日：2012-04-03

申请号：US11870529

申请日：2007-10-11

申请人： Ian F. Harris ,  Drew J. Dutton ,  Kenneth W. Gay

发明人： Ian F. Harris ,  Drew J. Dutton ,  Kenneth W. Gay

IPC分类号： G01R27/26

CPC分类号： G06F1/1679 ,  G06F1/1616 ,  H03K17/975 ,  H04M1/0245 ,  H04M2250/12 ,  H04W52/0251 ,  Y02D70/168

摘要： System and method for determining closure of an electronic device. The electronic device may include a top portion and a bottom portion, and may be connecting via a hinge or other closing mechanism. The top portion and/or the bottom portion may include one or more capacitive sensors which provide signals corresponding to physical contact and a controller coupled to the one or more capacitive sensors. The controller may operate to receive the signals from the one or more capacitive sensors, determine if the electronic device has been closed based on the received signals, and initiate a sequence of events corresponding to the closure of the electronic device. The sequence of events may result in the device entering a low power state.

摘要翻译： 用于确定电子设备闭合的系统和方法。 电子设备可以包括顶部和底部，并且可以经由铰链或其他关闭机构连接​​。 顶部和/或底部可以包括提供对应于物理接触的信号的一个或多个电容式传感器，以及耦合到一个或多个电容式传感器的控制器。 控制器可以操作以接收来自一个或多个电容式传感器的信号，基于接收到的信号确定电子设备是否已经被关闭，并且启动与电子设备的关闭对应的事件序列。 事件的顺序可能导致设备进入低功率状态。

公开(公告)号：US20110240189A1

公开(公告)日：2011-10-06

申请号：US13074394

申请日：2011-03-29

申请人： Drew J. Dutton

发明人： Drew J. Dutton

IPC分类号： B60B9/02

CPC分类号： B60B9/04 ,  B60B9/26

摘要： An interlocking, compressible spoke wheel system having a ring of paired spokes. The locking of left and right spokes into pairs provides improved tire displacement under loads. The left and right half wheels formed by sets of left spokes and right spokes. enable a novel mounting system for the wheel rim or tire to attach to the spoke system.

摘要翻译： 具有成对辐条环的互锁的可压缩辐条轮系统。 将左右轮辐锁定成对可以提供改善的载荷下的轮胎位移。 由左侧辐条和右辐条组成的左右半轮。 使得轮缘或轮胎的新型安装系统能够附接到辐条系统。

公开(公告)号：US07917741B2

公开(公告)日：2011-03-29

申请号：US11733599

申请日：2007-04-10

申请人： Drew J. Dutton ,  Alan D. Berenbaum ,  Richard E. Wahler ,  Raphael Weiss

发明人： Drew J. Dutton ,  Alan D. Berenbaum ,  Richard E. Wahler ,  Raphael Weiss

IPC分类号： G06F9/00 ,  G06F15/177 ,  G06F1/24 ,  G06F21/00 ,  G06F12/14 ,  G06F7/04 ,  G06F17/30 ,  G08B29/00

CPC分类号： G06F21/575

摘要： System and method for performing pre-boot security verification in a system that includes a host processor and memory, an embedded microcontroller with an auxiliary memory, e.g., an on-chip ROM, or memory controlled to prohibit user-tampering with the contents of the memory, and one or more pre-boot security components coupled to the embedded microcontroller. Upon power-up, but before host processor boot-up, the embedded microcontroller accesses the auxiliary memory and executes the program instructions to verify system security using the one or more pre-boot security components. The one or more pre-boot security components includes at least one identity verification component, e.g., a smart card, or a biometric sensor, e.g., a fingerprint sensor, a retinal scanner, and/or a voiceprint sensor, etc., and/or at least one system verification component, e.g., TPM, to query the system for system state information, and verify that the system has not been compromised.

摘要翻译： 用于在包括主处理器和存储器的系统中执行预引导安全验证的系统和方法，具有辅助存储器的嵌入式微控制器，例如片上ROM或被控制以禁止用户篡改内容的内存的存储器 存储器以及耦合到嵌入式微控制器的一个或多个预引导安全组件。 上电后，但在主机处理器启动之前，嵌入式微控制器访问辅助存储器并执行程序指令，以使用一个或多个预引导安全组件来验证系统的安全性。 一个或多个预引导安全组件包括至少一个身份验证组件，例如智能卡或生物测定传感器，例如指纹传感器，视网膜扫描器和/或声纹印刷传感器等，和/ 或至少一个系统验证组件（例如TPM）来查询系统的系统状态信息，并验证系统是否未被泄露。

公开(公告)号：US20090327678A1

公开(公告)日：2009-12-31

申请号：US11733599

申请日：2007-04-10

申请人： Drew J. Dutton ,  Alan D. Berenbaum ,  Richard E. Wahler ,  Raphael Weiss

发明人： Drew J. Dutton ,  Alan D. Berenbaum ,  Richard E. Wahler ,  Raphael Weiss

IPC分类号： G06F15/177

CPC分类号： G06F21/575

摘要： System and method for performing pre-boot security verification in a system that includes a host processor and memory, an embedded microcontroller with an auxiliary memory, e.g., an on-chip ROM, or memory controlled to prohibit user-tampering with the contents of the memory, and one or more pre-boot security components coupled to the embedded microcontroller. Upon power-up, but before host processor boot-up, the embedded microcontroller accesses the auxiliary memory and executes the program instructions to verify system security using the one or more pre-boot security components. The one or more pre-boot security components includes at least one identity verification component, e.g., a smart card, or a biometric sensor, e.g., a fingerprint sensor, a retinal scanner, and/or a voiceprint sensor, etc., and/or at least one system verification component, e.g., TPM, to query the system for system state information, and verify that the system has not been compromised.

摘要翻译： 用于在包括主处理器和存储器的系统中执行预引导安全验证的系统和方法，具有辅助存储器的嵌入式微控制器，例如片上ROM或被控制以禁止用户篡改内容的内存的存储器 存储器以及耦合到嵌入式微控制器的一个或多个预引导安全组件。 上电后，但在主机处理器启动之前，嵌入式微控制器访问辅助存储器并执行程序指令，以使用一个或多个预引导安全组件来验证系统的安全性。 一个或多个预引导安全组件包括至少一个身份验证组件，例如智能卡或生物测定传感器，例如指纹传感器，视网膜扫描器和/或声纹印刷传感器等，和/ 或至少一个系统验证组件（例如TPM）来查询系统的系统状态信息，并验证系统是否未被泄露。

公开(公告)号：US06061756A

公开(公告)日：2000-05-09

申请号：US89025

申请日：1998-06-02

申请人： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

发明人： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

IPC分类号： G06F13/368 ,  G06F13/372 ,  G06F13/40 ,  H04N21/238 ,  G06F13/38

CPC分类号： H04N21/238 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4013 ,  G06F13/4027

摘要： A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing and/or data packing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The data packing logic may optimally fill the bus with data having more or fewer bits than the bus. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

摘要翻译： 针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。 该系统包括标准本地系统总线或扩展总线，例如PCI总线，并且还可以包括专用实时总线或多媒体总线。 各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。 计算机系统包括耦合到扩展总线和/或多媒体总线中的一个或多个的字节分片和/或数据打包逻辑，其操作以允许不同的数据流同时使用不同的字节通道。 因此，字节分片总线允许不同的外设同时共享总线。 因此，字节分片逻辑可以将一个数据流分配给多媒体总线上的总字节通道的子集，并且用另一个数据流填充未使用的字节通道。 数据打包逻辑可以使用比总线更多或更少位的数据来最佳地填充总线。 因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。

公开(公告)号：US5761452A

公开(公告)日：1998-06-02

申请号：US617413

申请日：1996-03-18

申请人： Douglas A. Hooks ,  Drew J. Dutton

发明人： Douglas A. Hooks ,  Drew J. Dutton

IPC分类号： G06F13/364 ,  G06F13/00

CPC分类号： G06F13/364

摘要： An improved bus arbitration system comprising an information bus, first and second bus masters connected to the bus and a bus arbiter for controlling ownership of the bus. The first bus master is adapted to perform speculative pre-fetching and has a first REQ signal for requesting ownership of the bus and an SP signal for indicating when a bus ownership request is for a speculative pre-fetch. The second bus master has a second REQ signal for requesting ownership of the bus. The bus arbiter is configured such that when the first bus master asserts its REQ signal and its SP signal and the second bus master asserts its REQ signal, the bus arbiter assigns higher priority to the second bus master in response to the SP signal.

摘要翻译： 一种改进的总线仲裁系统，包括信息总线，连接到总线的第一和第二总线主机以及用于控制总线所有权的总线仲裁器。 第一总线主机适于执行推测性预取，并且具有用于请求总线所有权的第一REQ信号和用于指示总线所有权请求何时用于推测性预取的SP信号。 第二总线主机具有用于请求所有者总线的第二REQ信号。 总线仲裁器被配置为使得当第一总线主机断言其REQ信号及其SP信号，并且第二总线主机断言其REQ信号时，总线仲裁器响应于SP信号为第二总线主机分配更高的优先级。

公开(公告)号：US5754190A

公开(公告)日：1998-05-19

申请号：US481630

申请日：1995-06-07

申请人： Drew J. Dutton ,  Douglas D. Gephardt ,  Steven L. Belt ,  Brett B. Stewart ,  Rita M. Wisor

发明人： Drew J. Dutton ,  Douglas D. Gephardt ,  Steven L. Belt ,  Brett B. Stewart ,  Rita M. Wisor

IPC分类号： G06T9/00 ,  G06T13/00

CPC分类号： G06T9/001

摘要： A method and apparatus for transferring original data which includes images, between two stations located a distance apart, without actual transmission of the image portion of the data. A library of images are provided at each of the stations. The image to be transferred is processed into a description of the image which allows the reproduction of the image at the receiving end of the transmission using the images contained in the image library in the receiving station.

摘要翻译： 一种用于传送原始数据的方法和装置，其中包括位于距离分开的两个站之间的图像，而不实际传输数据的图像部分。 每个电台都提供图像库。 要传送的图像被处理成图像的描述，其允许使用包含在接收站中的图像库中的图像在传输的接收端再现图像。