公开(公告)号：US20090058429A1

公开(公告)日：2009-03-05

申请号：US11870529

申请日：2007-10-11

申请人： Ian F. Harris ,  Drew J. Dutton ,  Kenneth W. Gay

发明人： Ian F. Harris ,  Drew J. Dutton ,  Kenneth W. Gay

IPC分类号： G01R27/26

CPC分类号： G06F1/1679 ,  G06F1/1616 ,  H03K17/975 ,  H04M1/0245 ,  H04M2250/12 ,  H04W52/0251 ,  Y02D70/168

摘要： System and method for determining closure of an electronic device. The electronic device may include a top portion and a bottom portion, and may be connecting via a hinge or other closing mechanism. The top portion and/or the bottom portion may include one or more capacitive sensors which provide signals corresponding to physical contact and a controller coupled to the one or more capacitive sensors. The controller may operate to receive the signals from the one or more capacitive sensors, determine if the electronic device has been closed based on the received signals, and initiate a sequence of events corresponding to the closure of the electronic device. The sequence of events may result in the device entering a low power state.

摘要翻译： 用于确定电子设备闭合的系统和方法。 电子设备可以包括顶部和底部，并且可以经由铰链或其他关闭机构连接​​。 顶部和/或底部可以包括提供对应于物理接触的信号的一个或多个电容式传感器，以及耦合到一个或多个电容式传感器的控制器。 控制器可以操作以接收来自一个或多个电容式传感器的信号，基于接收到的信号确定电子设备是否已经被关闭，并且启动与电子设备的关闭对应的事件序列。 事件的顺序可能导致设备进入低功率状态。

公开(公告)号：US08149000B2

公开(公告)日：2012-04-03

申请号：US11870529

申请日：2007-10-11

申请人： Ian F. Harris ,  Drew J. Dutton ,  Kenneth W. Gay

发明人： Ian F. Harris ,  Drew J. Dutton ,  Kenneth W. Gay

IPC分类号： G01R27/26

CPC分类号： G06F1/1679 ,  G06F1/1616 ,  H03K17/975 ,  H04M1/0245 ,  H04M2250/12 ,  H04W52/0251 ,  Y02D70/168

摘要： System and method for determining closure of an electronic device. The electronic device may include a top portion and a bottom portion, and may be connecting via a hinge or other closing mechanism. The top portion and/or the bottom portion may include one or more capacitive sensors which provide signals corresponding to physical contact and a controller coupled to the one or more capacitive sensors. The controller may operate to receive the signals from the one or more capacitive sensors, determine if the electronic device has been closed based on the received signals, and initiate a sequence of events corresponding to the closure of the electronic device. The sequence of events may result in the device entering a low power state.

摘要翻译： 用于确定电子设备闭合的系统和方法。 电子设备可以包括顶部和底部，并且可以经由铰链或其他关闭机构连接​​。 顶部和/或底部可以包括提供对应于物理接触的信号的一个或多个电容式传感器，以及耦合到一个或多个电容式传感器的控制器。 控制器可以操作以接收来自一个或多个电容式传感器的信号，基于接收到的信号确定电子设备是否已经被关闭，并且启动与电子设备的关闭对应的事件序列。 事件的顺序可能导致设备进入低功率状态。

公开(公告)号：US07930576B2

公开(公告)日：2011-04-19

申请号：US11958601

申请日：2007-12-18

申请人： Ian F. Harris ,  Drew J. Dutton

发明人： Ian F. Harris ,  Drew J. Dutton

IPC分类号： G06F1/26 ,  G06F15/177

CPC分类号： G06F13/16

摘要： System and method for sharing a device, e.g., non-volatile memory, between a host processor and a microcontroller. In response to system state change to a first state wherein the microcontroller is assured safe access to the non-volatile memory (e.g., in response to power-on reset, system reset, sleep state, etc.), the microcontroller holds the system in the first state (e.g., system reset), and switches access to the non-volatile memory from the processor to the microcontroller. While the system is held in the first state, the microcontroller accesses the device (e.g., non-volatile memory), e.g., fetches program instructions/data from the non-volatile memory and loads the program instructions/data into a memory of the microcontroller. After the access, the microcontroller changes or allows change of the system state, e.g., switches access to the device, e.g., the non-volatile memory, from the microcontroller to the processor, and releases the system from the first state.

摘要翻译： 用于在主处理器和微控制器之间共享设备（例如，非易失性存储器）的系统和方法。 响应于系统状态改变到第一状态，其中微控制器被安全地访问非易失性存储器（例如，响应于上电复位，系统复位，睡眠状态等），微控制器将系统保持在 第一个状态（例如，系统复位），并切换从处理器到微控制器的非易失性存储器的访问。 当系统处于第一状态时，微控制器访问设备（例如，非易失性存储器），例如从非易失性存储器获取程序指令/数据，并将程序指令/数据加载到微控制器的存储器中 。 在访问之后，微控制器改变或允许系统状态的改变，例如，将从该微控制器的设备（例如，非易失性存储器）的访问切换到处理器，并将系统从第一状态释放。

公开(公告)号：US20080256374A1

公开(公告)日：2008-10-16

申请号：US11958601

申请日：2007-12-18

申请人： Ian F. Harris ,  Drew J. Dutton

发明人： Ian F. Harris ,  Drew J. Dutton

IPC分类号： G06F12/00 ,  G06F1/32

CPC分类号： G06F13/16

摘要： System and method for sharing a device, e.g., non-volatile memory, between a host processor and a microcontroller. In response to system state change to a first state wherein the microcontroller is assured safe access to the non-volatile memory (e.g., in response to power-on reset, system reset, sleep state, etc.), the microcontroller holds the system in the first state (e.g., system reset), and switches access to the non-volatile memory from the processor to the microcontroller. While the system is held in the first state, the microcontroller accesses the device (e.g., non-volatile memory), e.g., fetches program instructions/data from the non-volatile memory and loads the program instructions/data into a memory of the microcontroller. After the access, the microcontroller changes or allows change of the system state, e.g., switches access to the device, e.g., the non-volatile memory, from the microcontroller to the processor, and releases the system from the first state.

摘要翻译： 用于在主处理器和微控制器之间共享设备（例如，非易失性存储器）的系统和方法。 响应于系统状态改变到第一状态，其中微控制器被安全地访问非易失性存储器（例如，响应于上电复位，系统复位，睡眠状态等），微控制器将系统保持在 第一个状态（例如，系统复位），并切换从处理器到微控制器的非易失性存储器的访问。 当系统处于第一状态时，微控制器访问设备（例如，非易失性存储器），例如从非易失性存储器获取程序指令/数据，并将程序指令/数据加载到微控制器的存储器中 。 在访问之后，微控制器改变或允许系统状态的改变，例如，将从该微控制器的设备（例如，非易失性存储器）的访问切换到处理器，并将系统从第一状态释放。

公开(公告)号：US08239603B2

公开(公告)日：2012-08-07

申请号：US11417391

申请日：2006-05-03

申请人： Drew J. Dutton ,  Alan D. Berenbaum ,  Raphael Weiss

发明人： Drew J. Dutton ,  Alan D. Berenbaum ,  Raphael Weiss

IPC分类号： G06F13/40

CPC分类号： G06F13/4027

摘要： A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.

摘要翻译： 一种包括序列化二次总线架构的系统。 该系统可以包括LPC总线，I / O控制器，串行化辅助总线和至少一个从设备。 LPC总线可以连接到I / O控制器，并且至少一个从设备可以经由串行辅助总线连接到I / O控制器。 串行次级总线相对于LPC总线的引脚数量减少。 I / O控制器可以从LPC总线接收总线事务。 I / O控制器可以通过辅助总线将LPC总线事务转换和转发到至少一个设备。 I / O控制器可以包括处理单元。 处理单元可以启动用于至少一个从设备的总线事务。 I / O控制器还可以包括总线仲裁单元。 总线仲裁单元可以仲裁处理单元和LPC总线之间的辅助总线的所有权。

公开(公告)号：US6047350A

公开(公告)日：2000-04-04

申请号：US989329

申请日：1997-12-11

申请人： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

发明人： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

IPC分类号： G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/40 ,  H04N21/238 ,  G06F13/38

CPC分类号： H04N21/238 ,  G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4013 ,  G06F13/4022 ,  G06F13/4027

摘要： A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

摘要翻译： 针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。 该系统包括标准本地系统总线或扩展总线，例如PCI总线，并且还可以包括专用实时总线或多媒体总线。 各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。 计算机系统包括耦合到一个或多个扩展总线和/或多媒体总线的字节分片逻辑，其操作以允许不同的数据流同时使用不同的字节通道。 因此，字节分片多媒体总线允许不同的外设同时共享总线。 因此，字节分片逻辑可以将一个数据流分配给多媒体总线上的总字节通道的子集，并且用另一个数据流填充未使用的字节通道。 因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。

公开(公告)号：US5923887A

公开(公告)日：1999-07-13

申请号：US650570

申请日：1996-05-20

申请人： Drew J. Dutton

发明人： Drew J. Dutton

IPC分类号： G06F13/24 ,  G06F9/46

CPC分类号： G06F13/24

摘要： An improved programmable interrupt controller for use in a computer system including one or more interrupt service providers (ISPs), usually central processing units (CPUs). At least one CPU and a main memory system are coupled to a host bus. A bus bridge device couples the host bus to the expansion bus. At least one I/O device is coupled to the expansion bus and generates an interrupt request signal. The bus bridge and other bus devices may also generate interrupt request signals. A programmable interrupt controller receives the interrupt requests and provides processor interrupt signals as well as information regarding resource requirements necessary for servicing the interrupts to the one or more CPUs. The programmable interrupt controller also receives interrupt acknowledge signals from the one or more CPUs.

摘要翻译： 一种改进的可编程中断控制器，用于包括一个或多个中断服务提供商（ISP）的计算机系统，通常是中央处理单元（CPU）。 至少一个CPU和主存储器系统耦合到主机总线。 总线桥装置将主机总线耦合到扩展总线。 至少一个I / O设备被耦合到扩展总线并产生中断请求信号。 总线桥和其他总线设备也可能产生中断请求信号。 可编程中断控制器接收中断请求并提供处理器中断信号以及关于维护一个或多个CPU的中断所需的资源需求的信息。 可编程中断控制器还从一个或多个CPU接收中断确认信号。

公开(公告)号：US5819080A

公开(公告)日：1998-10-06

申请号：US582125

申请日：1996-01-02

申请人： Drew J. Dutton ,  David S. Christie

发明人： Drew J. Dutton ,  David S. Christie

IPC分类号： G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/30094 ,  G06F12/0804 ,  G06F12/0888 ,  G06F9/30185 ,  G06F9/383 ,  G06F9/3846

摘要： A microprocessor is provided including a branch prediction unit configured to select one of multiple sets of condition flags for use by a branch instruction according to the segment register override prefix byte which may be included with the instruction. Branch instructions may be scheduled distant from the instruction which sets the condition flags tested by the branch instruction. Numerous instructions may be placed between the two instructions, such that the condition flags may be available at the time the instruction is fetched. The branch instruction may be executed without stalling until the condition flags are available. In another embodiment, the branch prediction unit is configured to predict the direction a branch instruction may take according to a branch prediction scheme. Additionally, upon detection of a segment override prefix byte, the branch prediction unit uses an alternative branch prediction scheme. The alternative branch prediction scheme may be to predict the branch taken if a particular segment register override prefix byte is detected, and to predict the branch not taken if another particular segment register override prefix byte is detected.

摘要翻译： 提供了一种微处理器，其包括分支预测单元，该分支预测单元被配置为根据可能包含在该指令中的分段寄存器覆盖前缀字节来选择由分支指令使用的多组条件标志中的一个。 分支指令可以被调度为远离设置由分支指令测试的条件标志的指令。 可以在两个指令之间放置许多指令，使得条件标志在获取指令时可用。 分支指令可以在不停止的情况下执行，直到条件标志可用。 在另一实施例中，分支预测单元被配置为根据分支预测方案来预测分支指令可以采用的方向。 此外，在检测到段重写前缀字节时，分支预测单元使用替代分支预测方案。 替代分支预测方案可以是预测如果检测到特定分段寄存器覆盖前缀字节所采取的分支，并且如果检测到另一个特定分段寄存器覆盖前缀字节，则预测未采用的分支。

公开(公告)号：US5317715A

公开(公告)日：1994-05-31

申请号：US911783

申请日：1992-07-10

申请人： William M. Johnson ,  Timothy A. Olson ,  Drew J. Dutton ,  Sherman Lee ,  David W. Stoenner

发明人： William M. Johnson ,  Timothy A. Olson ,  Drew J. Dutton ,  Sherman Lee ,  David W. Stoenner

IPC分类号： G06F13/28 ,  G06F13/40 ,  G06F13/00 ,  G06F13/23

CPC分类号： G06F13/4013 ,  G06F13/28

摘要： Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ("CPU"), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ("DTC"), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.

摘要翻译： 公开了用于向简化指令集计算机（RISC）系统的本地总线传输数据的方法和装置，包括至少一个中央处理器（“CPU”）的第一组高性能设备， 和远程总线，第二组相对较低性能的设备以不限制RISC处理器性能的方式连接到该远程总线。 根据本发明的优选实施例，公开了一种RISC架构，其包括新颖的数据传输控制器（“DTC”）或一组DTC，适用于在高性能本地总线与一个或多个本地总线之间执行上述数据传输功能 通常具有不同（和较低）性能特征的完整子系统或外设的远程总线。 由此产生的RISC节点允许商业化的外围设备和子系统与高性能RISC处理器配合使用，而不会限制RISC系统的性能。

公开(公告)号：US08149001B2

公开(公告)日：2012-04-03

申请号：US12359056

申请日：2009-01-23

申请人： Simeon K. Iliev ,  Drew J. Dutton

发明人： Simeon K. Iliev ,  Drew J. Dutton

IPC分类号： G01R27/26

CPC分类号： G06K9/0002

摘要： Low cost fingerprint system having a single chip solution includes a circuit board, a fingerprint sensor array fabricated onto a first surface of the circuit board, and an integrated circuit die for processing information received from the fingerprint sensor array is mounted directly to a second surface of the circuit board. The integrated circuit die may be electrically connected to the sensor by, for example, vias in the circuit board.

摘要翻译： 具有单芯片解决方案的低成本指纹系统包括电路板，制造在电路板的第一表面上的指纹传感器阵列和用于处理从指纹传感器阵列接收的信息的集成电路管芯直接安装在第二表面 电路板。 集成电路管芯可以通过例如电路板中的通孔电连接到传感器。