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1.发明申请Information Handling System with Processing System, Low-power Processing System and Shared Resources 有权具有处理系统，低功耗处理系统和共享资源的信息处理系统公开(公告)号：US20120013795A1
公开(公告)日：2012-01-19
申请号：US13242635
申请日：2011-09-23
CPC分类号： G06F1/3203 , G06F1/3293 , Y02D10/122 , Y02D50/20
摘要： An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.
摘要翻译： 信息处理系统包括处理系统，低功率处理系统和芯片组。 处理系统被配置为使用被配置为为处理系统的共享资源和处理系统的非共享资源供电的电力系统来操作，并且在处理系统的减少的操作状态期间禁用非共享资源。 低功率处理系统被配置为在低功率处理系统的操作期间访问处理系统的共享资源，其中低功率处理系统的操作与处理系统的操作分离。 芯片组包括处理系统的处理器，并且可操作以在处理系统的操作期间启用，其中处理器被配置为在低功率处理系统的操作期间被禁用。
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2.发明授权Microprocessor including an interrupt polling unit configured to poll external devices for interrupts using interrupt acknowledge bus transactions 失效微处理器包括一个中断轮询单元，配置为使用中断确认总线事务轮询外部设备进行中断
公开(公告)号：US5687381A
公开(公告)日：1997-11-11
申请号：US599603
申请日：1996-02-09
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes a periodic interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transaction returns an interrupt vector indicative of an interrupt service routine, then the microprocessor executes the interrupt service routine. The number of interrupt acknowledge bus transactions associated with the interrupt is reduced from two to one, and the microprocessor effectively prefetches the interrupt service routine before the interrupt is actually signaled. In one embodiment, the interrupt polling unit causes an interrupt acknowledge bus transaction to occur at the expiration of a programmable time interval. Another embodiment of the interrupt polling unit causes an interrupt acknowledge bus transaction subsequent to the occurrence of a bus transaction programmed by the user.
摘要翻译： 提供了包括在微处理器的总线接口单元内的中断轮询单元。 中断轮询单元导致周期性中断确认总线事务发生。 如果接收到中断确认总线事务的中断控制器返回指示中断服务程序的中断向量，则微处理器执行中断服务程序。 与中断相关联的中断确认总线事务数量从两个减少到一个，并且微处理器在实际发出中断之前有效地预取中断服务程序。 在一个实施例中，中断轮询单元导致在可编程时间间隔期满时发生中断确认总线事务。 中断轮询单元的另一实施例在由用户编程的总线事务发生之后导致中断确认总线事务。
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3.发明授权Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program 失效用于以一种执行程序不可见的方式维持一个中断屏蔽寄存器与另一个中断屏蔽寄存器一致的装置
公开(公告)号：US5551033A
公开(公告)日：1996-08-27
申请号：US893432
申请日：1992-06-04
申请人： Mark J. Foster , Saifuddin T. Fakhruddin , James L. Walker , Matthew B. Mendelow , Jiming Sun , Rodman S. Brahman , Michael P. Krau , Brian D. Willoughby , Michael D. Maddix , Steven L. Belt , Scott A. Hovey , Mark A. Ruthenbeck
发明人： Mark J. Foster , Saifuddin T. Fakhruddin , James L. Walker , Matthew B. Mendelow , Jiming Sun , Rodman S. Brahman , Michael P. Krau , Brian D. Willoughby , Michael D. Maddix , Steven L. Belt , Scott A. Hovey , Mark A. Ruthenbeck
CPC分类号： G06F9/4812 , G06F1/24 , G06F1/3203 , G06F1/324 , G06F9/463 , Y02B60/1217 , Y02B60/144
摘要： A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. The system includes a first interrupt mask register having a bit for indicating whether an interrupt is to be recognized by the processor, a second interrupt mask register having a bit for indicating whether the interrupt is to be recognized by a further circuit, and an arrangement responsive to a load of the first mask register for conforming the bit of the second mask register to the bit of the first mask register in a manner invisible to an application program being executed by the processor.
摘要翻译： 膝上型计算机系统包括能够以受限制和无限制模式操作的保护模式微处理器，并且响应于预定条件的装置保存来自处理器的信息，然后强制地将处理器切换到其无限制操作模式。 该系统包括第一中断屏蔽寄存器，该第一中断屏蔽寄存器具有用于指示处理器是否识别中断的位;第二中断屏蔽寄存器，具有用于指示该中断是否被另一电路识别的位，以及响应于 到第一掩模寄存器的负载，用于使第二掩模寄存器的位与第一掩模寄存器的位以对于由处理器执行的应用程序不可见的方式进行匹配。
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公开(公告)号：US06219754B1
公开(公告)日：2001-04-17
申请号：US08994489
申请日：1997-12-19
IPC分类号： G06F1200
CPC分类号： G06F12/0875
摘要： A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.
摘要翻译： 在中央处理单元和周边单元之间的专用总线，例如驱动视频显示器的图形控制器，在中央处理单元内发生信号处理的环境中提供增强的能力。 专用总线减轻了诸如PCI总线的其他数据总线，需要传送大量数据，例如解压缩的视频数据。 所得到的系统支持解压缩视频数据的高带宽传输，实现高分辨率24位全动态视频和多数据流视频。
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5.发明授权公开(公告)号：US06193422B1
公开(公告)日：2001-02-27
申请号：US08264182
申请日：1994-06-22
申请人： Steven L. Belt , Robert J. Grabon , Chandrakant H. Pandya , Jiming Sun , Neysa K. Terry-Gray , Min E. Lee , Norman M. Hack
发明人： Steven L. Belt , Robert J. Grabon , Chandrakant H. Pandya , Jiming Sun , Neysa K. Terry-Gray , Min E. Lee , Norman M. Hack
IPC分类号： G06F1310
CPC分类号： G06F1/24 , G06F1/3203
摘要： A portable computer system includes an input device such as a keyboard, a display, and a processor which is operable in a normal operational mode and in a reduced power mode, the processor carrying out program execution in each of the normal operational mode and reduced power mode. A timing arrangement switches the processor from its normal operational mode to its reduced power mode in response to the absence of any of a plurality of predetermined events during a predetermined time interval, the predetermined events including actuation of keys on the keyboard and transmission of information to the video display.
摘要翻译： 便携式计算机系统包括诸如键盘，显示器和处理器的输入设备，其可以在正常操作模式和降低功率模式下操作，处理器在每个正常操作模式和降低的功率下执行程序执行 模式。 响应于在预定时间间隔期间不存在多个预定事件中的任何一个，定时装置将处理器从其正常操作模式切换到其降低功率模式，预定事件包括键盘上的键的激活和信息的传送 视频显示。
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6.发明授权Interrupt for a protected mode microprocessor which facilitates transparent entry to and exit from suspend mode 失效用于保护模式微处理器的中断，便于透明进入和退出挂起模式
公开(公告)号：US5652890A
公开(公告)日：1997-07-29
申请号：US173380
申请日：1993-12-23
申请人： Mark J. Foster , Saifuddin T. Fakhruddin , James L. Walker , Matthew B. Mendelow , Jiming Sun , Rodman S. Brahman , Michael P. Krau , Brian D. Willoughby , Michael D. Maddix , Steven L. Belt , Scott A. Hovey , Mark A. Ruthenbeck
发明人： Mark J. Foster , Saifuddin T. Fakhruddin , James L. Walker , Matthew B. Mendelow , Jiming Sun , Rodman S. Brahman , Michael P. Krau , Brian D. Willoughby , Michael D. Maddix , Steven L. Belt , Scott A. Hovey , Mark A. Ruthenbeck
CPC分类号： G06F9/4812 , G06F1/24 , G06F1/324 , G06F9/463 , Y02B60/1217
摘要： A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. When running a multi-tasking operating system where an application program is being executed in a restricted mode, a suspend/resume operation can be carried out in which the system is substantially powered down and then powered back up, and will resume the interrupted application with the restricted mode back in effect. Further, set-up changes such as adjustment of the processor speed can be made without exiting the application program running in the restricted mode.
摘要翻译： 膝上型计算机系统包括能够以受限制和无限制模式操作的保护模式微处理器，并且响应于预定条件的装置保存来自处理器的信息，然后强制地将处理器切换到其无限制操作模式。 当在受限制的模式下运行应用程序的多任务操作系统时，可以执行暂停/恢复操作，其中系统基本上断电然后重新上电，并且将以 限制模式有效。 此外，可以在不退出在限制模式下运行的应用程序的情况下进行诸如调整处理器速度的设置更改。
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7.发明授权
公开(公告)号：US5625829A
公开(公告)日：1997-04-29
申请号：US276250
申请日：1994-07-18
IPC分类号： G06F15/173 , G06F1/16 , G06F13/36 , G06F13/364 , G06F13/40 , G06F3/00
CPC分类号： G06F13/364 , G06F1/1632 , G06F13/4036 , G06F13/4081
摘要： A dockable computer system is capable of performing symmetrical multi-processing operations. More particularly, the dockable computer system includes a portable computer and a host station (docking station), each including a resident CPU. The dockable computer system is capable of operating in a docked state in which the portable computer is physically joined with the host station and an undocked state in which the portable computer is physically separate from the host station. In the docked state, the dockable computer system is capable of performing demanding computational tasks such as video conferencing as one of the CPUs in either the portable computer or host station is dedicated to the video conferencing operation. The dockable computer system preferably includes a communication channel for transmitting multi-processing support signals between the portable computer and the host station. Multi-processing support signals include synchronization signals, cache coherency signals, and interrupt distribution signals such as the LOCK signal, PLOCK signal, FLUSH signal, EADS signal, INTR signal or INTACK signal. The communication channel may be a dedicated bus or may be provided through a docking bridge between the portable computer and host station. The dockable computer system advantageously optimizes CPU resources when the dockable computer system is in a docked state.
摘要翻译： 可停靠的计算机系统能够执行对称的多处理操作。 更具体地，可停靠的计算机系统包括便携式计算机和主机站（对接站），每个都包括驻留的CPU。 可停靠的计算机系统能够在对接状态下操作，其中便携式计算机与主机站物理连接，并且其中便携式计算机在物理上与主机站分离的未停靠状态。 在对接状态下，可停靠的计算机系统能够执行诸如视频会议的苛刻的计算任务，因为便携式计算机或主机站中的一个CPU专用于视频会议操作。 对接计算机系统优选地包括用于在便携式计算机和主机站之间传送多处理支持信号的通信信道。 多处理支持信号包括同步信号，高速缓存一致性信号和中断分配信号，例如LOCK信号，PLOCK信号，FLUSH信号，EADS信号，INTR信号或INTACK信号。 通信信道可以是专用总线，或者可以通过便携式计算机和主机站之间的对接桥提供。 可对接计算机系统有利地优化当可停靠的计算机系统处于对接状态时的CPU资源。
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公开(公告)号：US5303171A
公开(公告)日：1994-04-12
申请号：US865048
申请日：1992-04-03
CPC分类号： G06F1/324 , G06F1/24 , G06F1/3203 , Y02B60/1217
摘要： A portable computer system includes a housing, a lid supported on the housing for movement between open and closed positions, a keyboard supported on the housing below the lid, and a display provided on the lid. When the lid is opened, the keyboard is accessible and the display is visible, whereas when the lid is closed the keyboard and display are hidden and protected. The computer system includes a processor disposed within the housing and having a first operational mode in which it executes instructions and a second operational mode in which it is in a reduced power suspend state from which it can automatically exit in response to a predetermined condition. The system includes an arrangement responsive to closing of the lid when the processor is in its first operational state for switching the processor to its second operational state.
摘要翻译： 便携式计算机系统包括壳体，支撑在壳体上用于在打开和关闭位置之间运动的盖子，支撑在盖子下方的壳体上的键盘以及设置在盖子上的显示器。 当盖子打开时，键盘可以访问并且显示屏是可见的，而当盖子关闭时，键盘和显示器被隐藏并被保护。 计算机系统包括设置在壳体内的处理器，并且具有第一操作模式，其中它执行指令和第二操作模式，其中它处于能够响应于预定条件自动退出的降低功率暂停状态。 当处理器处于其第一操作状态以便将处理器切换到其第二操作状态时，系统包括响应于关闭盖子的装置。
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9.发明申请公开(公告)号：US20120311364A1
公开(公告)日：2012-12-06
申请号：US13587048
申请日：2012-08-16
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3293 , Y02D10/122 , Y02D50/20
摘要： An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.
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公开(公告)号：US5754190A
公开(公告)日：1998-05-19
申请号：US481630
申请日：1995-06-07
CPC分类号： G06T9/001
摘要： A method and apparatus for transferring original data which includes images, between two stations located a distance apart, without actual transmission of the image portion of the data. A library of images are provided at each of the stations. The image to be transferred is processed into a description of the image which allows the reproduction of the image at the receiving end of the transmission using the images contained in the image library in the receiving station.
摘要翻译： 一种用于传送原始数据的方法和装置，其中包括位于距离分开的两个站之间的图像，而不实际传输数据的图像部分。 每个电台都提供图像库。 要传送的图像被处理成图像的描述，其允许使用包含在接收站中的图像库中的图像在传输的接收端再现图像。
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