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    Low current switching magnetic tunnel junction design for magnetic memory using domain wall motion
    21.
    发明授权
    Low current switching magnetic tunnel junction design for magnetic memory using domain wall motion 有权
    低电流切换磁隧道结设计，用于使用畴壁运动的磁存储器

    公开(公告)号：US08164947B2

    公开(公告)日：2012-04-24

    申请号：US12985028

    申请日：2011-01-05

    Applicant: Rajiv Yadav Ranjan ,  Roger Klaus Malmhall ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Roger Klaus Malmhall ,  Parviz Keshtbod

    IPC: G11C11/00 ,  G11C11/14 ,  G11C11/15

    CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  H01L43/08

    Abstract: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

    Abstract translation: 公开了一种包括自由层，两个堆叠和磁性隧道结的多状态低电流切换磁存储元件（磁存储元件）。 堆叠和磁性隧道结设置在自由层的表面上，磁性隧道结位于堆叠之间。 堆叠在自由层内引导磁畴，产生自由层畴壁。 从堆栈传递到堆栈的电流推动域壁，重新定位自由层内的域壁。 畴壁相对于磁性隧道结的位置对应于唯一的电阻值，并且将电流从堆叠传递到磁性隧道结读取磁存储元件的电阻。 因此，可以通过移动域壁来实现唯一的记忆状态。

    LOW COST MULTI-STATE MAGNETIC MEMORY
    23.
    发明申请
    LOW COST MULTI-STATE MAGNETIC MEMORY 有权
    低成本多状态磁记忆

    公开(公告)号：US20110305078A1

    公开(公告)日：2011-12-15

    申请号：US13216997

    申请日：2011-08-24

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    IPC: G11C11/14 ,  H01L29/82

    CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607

    Abstract: A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer.

    Abstract translation: 多状态电流切换磁存储元件具有磁隧道结（MTJ），用于存储多于一位的信息。 MTJ包括固定层，阻挡层和不均匀的自由层。 在一个实施例中，当每个单元具有2位时，当四个不同电平的电流之一被施加到存储元件时，所施加的电流使MTJ的非均匀自由层切换到四个不同的磁状态之一。 MTJ的宽开关电流分布是非均匀自由层的宽晶粒尺寸分布的结果。

    Low cost multi-state magnetic memory
    25.
    发明授权
    Low cost multi-state magnetic memory 有权
    低成本多状态磁存储器

    公开(公告)号：US08018011B2

    公开(公告)日：2011-09-13

    申请号：US11860467

    申请日：2007-09-24

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    IPC: H01L29/82 ,  G11C11/00

    CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607

    Abstract: A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer.

    Abstract translation: 多状态电流切换磁存储元件具有磁隧道结（MTJ），用于存储多于一位的信息。 MTJ包括固定层，阻挡层和不均匀的自由层。 在一个实施例中，当每个单元具有2位时，当四个不同电平的电流之一被施加到存储元件时，所施加的电流使MTJ的非均匀自由层切换到四个不同的磁状态之一。 MTJ的宽开关电流分布是非均匀自由层的宽晶粒尺寸分布的结果。

    Nonvolatile memory using flexible erasing methods and method and system for using same
    27.
    发明授权
    Nonvolatile memory using flexible erasing methods and method and system for using same 有权
    非易失性存储器采用灵活的擦除方法和方法及系统使用

    公开(公告)号：US06411546B1

    公开(公告)日：2002-06-25

    申请号：US09565517

    申请日：2000-05-05

    Applicant: Petro Estakhri ,  Siamack Nemazie ,  Mahmud Assar ,  Parviz Keshtbod

    Inventor： Petro Estakhri ,  Siamack Nemazie ,  Mahmud Assar ,  Parviz Keshtbod

    IPC: G11C1604

    CPC classification number: G11C16/102 ,  G06F3/0604 ,  G06F3/0607 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0246 ,  G11C8/12 ,  G11C16/08

    Abstract: An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field and each sector stored within a row of the memory array. A controller circuit is coupled to a host circuit and is operative to perform erase operations on the nonvolatile memory array, the controller circuit erases an identified sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are caused to be erased separately.

    Abstract translation: 公开了本发明的实施例，其包括用于控制对由行和列组成的非易失性存储器阵列执行的擦除操作的非易失性存储器系统，非易失性存储器阵列存储组织成块的数字信息，每个块具有一个或多个信息扇区 并且每个扇区具有用户数据字段和扩展字段，并且每个扇区存储在存储器阵列的行内。 控制器电路耦合到主机电路并且可操作以对非易失性存储器阵列执行擦除操作，控制器电路擦除所识别的具有特定用户数据字段和特定扩展字段的信息扇区，其中特定用户字段和特定用户字段 扩展字段被分别擦除。

    Spacer flash cell device with vertically oriented floating gate
    28.
    发明授权
    Spacer flash cell device with vertically oriented floating gate 失效
    具有垂直定向浮动栅极的隔板闪存单元

    公开(公告)号：US5479368A

    公开(公告)日：1995-12-26

    申请号：US129866

    申请日：1993-09-30

    Applicant: Parviz Keshtbod

    Inventor： Parviz Keshtbod

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

    Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a first doped polysilicon layer. The field oxide is selectively removed. A gate oxide is grown and a second polysilicon layer is formed and then etched to form spacers along the edges of the first polysilicon/second insulator structure. The second polysilicon is selectively etched and a tunneling insulator layer is formed thereover. A third polysilicon layer is formed over the tunneling insulator.

    Abstract translation: 闪存EPROM单元在编程期间通过在浮动栅极和位线之间提供垂直耦合而具有减小的单元尺寸。 擦除操作是通过将电子从Poly间隔物的尖端引导到控制栅极进行的。 单元被适配成使得阵列内的每个单元的源极是相邻单元的源极，漏极是另一相邻单元的漏极。 通过在优选为场氧化物的第一绝缘体中的开口将漏区形成为衬底而形成电池。 第二绝缘体沉积在第一绝缘体上方，在衬底上并且沿着开口的侧壁，并且优选地是薄层，使得开口被薄绝缘层覆盖。 绝缘开口填充有第一掺杂多晶硅层。 有选择地去除场氧化物。 生长栅极氧化物并形成第二多晶硅层，然后蚀刻以沿着第一多晶硅/第二绝缘体结构的边缘形成间隔物。 选择性地蚀刻第二多晶硅，并在其上形成隧穿绝缘体层。 在隧道绝缘体上形成第三多晶硅层。

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