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    System-On-A-Chip Employing A Network Of Nodes That Utilize Receive Side Flow Control Over Channels For Messages Communicated Therebetween
    21.
    发明申请
    System-On-A-Chip Employing A Network Of Nodes That Utilize Receive Side Flow Control Over Channels For Messages Communicated Therebetween 审中-公开
    系统级芯片采用利用接收侧流控制的节点网络对于其间通信的消息

    公开(公告)号：US20100191814A1

    公开(公告)日：2010-07-29

    申请号：US12639326

    申请日：2009-12-16

    申请人： Marco Heddes ,  Massimo Ravasi ,  Rakesh Kumar Malik ,  Michael Singngee Yeo

    发明人： Marco Heddes ,  Massimo Ravasi ,  Rakesh Kumar Malik ,  Michael Singngee Yeo

    IPC分类号： G06F15/16

    CPC分类号： G06F15/16

    摘要： An integrated circuit an array of nodes linked by an on-chip communication network. Messages are communicated between nodes utilizing logical channels representing hardware resources at the associated nodes. A given logical channel is associated with a receiver node and a transmitter node. The receiver node is adapted to send flow control messages to the transmitter node. The flow control messages include credits that identify hardware resources of the receiver node that are available for receiving messages over the given logical channel. The transmitter node is adapted to maintain a running total of the credits included as part of the flow control messages communicated from the receiver node and to initiate transmission of messages to the receiver node in accordance with the running total of credits maintained at the transmitter node. In the preferred embodiment, the transmitter node is adapted to initiate transmission of a message to the receiver node only if the total number of credits maintained at the transmitter node is sufficient to store the message at the receiver node. A given credit can include an address generated by a receiver node and representing an address in the local memory of the receiver node for storing data. The transmitter node transmits the address of the given credit to the receiver node for storing data therein.

    摘要翻译： 集成电路，由片上通信网络链接的节点阵列。 使用表示相关节点处的硬件资源的逻辑信道在节点之间传送消息。 给定的逻辑信道与接收机节点和发射机节点相关联。 接收机节点适于向发射机节点发送流量控制消息。 流控制消息包括识别接收机节点的硬件资源的信用，该硬件资源可用于通过给定逻辑信道接收消息。 发射机节点适于维持作为从接收机节点传送的流控制消息的一部分包括的信用的运行总计，并且根据在发射机节点处保持的信用的运行总计来发起消息到接收机节点的传输。 在优选实施例中，只有在发射机节点处保存的信用总数足以在接收机节点处存储消息时，发射机节点适于发起消息到接收机节点的传输。 给定的信用可以包括由接收器节点生成的地址并且表示用于存储数据的接收器节点的本地存储器中的地址。 发射机节点将给定信用的地址发送到接收机节点，用于在其中存储数据。

    Chip to chip interface for interconnecting chips
    24.
    发明授权
    Chip to chip interface for interconnecting chips 失效
    用于互连芯片的芯片到芯片接口

    公开(公告)号：US06910092B2

    公开(公告)日：2005-06-21

    申请号：US10016800

    申请日：2001-12-10

    申请人： Jean Louis Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Joseph Franklin Logan ,  Tolga Ozguner

    发明人： Jean Louis Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Joseph Franklin Logan ,  Tolga Ozguner

    IPC分类号： G06F13/00 ,  G06F13/14 ,  G06F13/42

    CPC分类号： G06F13/4265

    摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.

    摘要翻译： 网络处理器（NP）由多个可操作耦合的芯片形成。 NP包括耦合到耦合到数据流芯片的数据流芯片和数据存储存储器的网络处理器复合（NPC）芯片。 可选的调度器芯片耦合到数据流芯片。 命名的组件被复制以创建对称的入口和出口结构。 芯片之间的通信由一对芯片到芯片宏提供，其中每一个可操作地位于一个芯片上，并且芯片到芯片总线接口可操作地将芯片连接到芯片宏。

    Priority based bandwidth allocation within real-time and non-real time traffic streams
    25.
    发明授权
    Priority based bandwidth allocation within real-time and non-real time traffic streams 有权
    实时和非实时业务流中基于优先级的带宽分配

    公开(公告)号：US07872968B2

    公开(公告)日：2011-01-18

    申请号：US11608295

    申请日：2006-12-08

    申请人： Brahmanand Kumar Gorti ,  Marco Heddes ,  Clark Debs Jeffries ,  Andreas Kind ,  Michael Steven Siegel

    发明人： Brahmanand Kumar Gorti ,  Marco Heddes ,  Clark Debs Jeffries ,  Andreas Kind ,  Michael Steven Siegel

    IPC分类号： G01R31/08 ,  H04L12/28

    CPC分类号： H04L47/6215 ,  H04L47/10 ,  H04L47/2416 ,  H04L47/2433 ,  H04L47/30 ,  H04L47/32 ,  H04L47/50 ,  H04L47/52 ,  H04L47/56

    摘要： A method and system for transmitting packets in a packet switching network. Packets received by a packet processor may be prioritized based on the urgency to process them. Packets that are urgent to be processed may be referred to as real-time packets. Packets that are not urgent to be processed may be referred to as non-real-time packets. Real-time packets have a higher priority to be processed than non-real-time packets. A real-time packet may either be discarded or transmitted into a real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time queue congestion conditions. A non-real-time packet may either be discarded or transmitted into a non-real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time and non-real-time queue congestion conditions.

    摘要翻译： 一种用于在分组交换网络中传送分组的方法和系统。 可以基于处理它们的紧急性来优先考虑由分组处理器接收的分组。 紧急处理的数据包可以称为实时数据包。 不紧急处理的数据包可能被称为非实时数据包。 实时数据包的优先级要高于非实时数据包。 可以根据其值优先级，该值优先级的最小和最大速率以及当前实时队列拥塞条件，将实时分组丢弃或传输到实时队列中。 可以基于其值优先级，该值优先级的最小和最大速率以及当前的实时和非实时队列拥塞将非实时分组丢弃或发送到非实时队列 条件。

    Semaphore management subsystem for use with multi-thread processor systems
    27.
    发明授权
    Semaphore management subsystem for use with multi-thread processor systems 失效
    用于多线程处理器系统的信号量管理子系统

    公开(公告)号：US07454753B2

    公开(公告)日：2008-11-18

    申请号：US10179860

    申请日：2002-06-25

    申请人： Gordon Taylor Davis ,  Marco Heddes ,  Steven Kenneth Jenkins ,  Ross Boyd Leavens ,  Robert Brian Likovich, Jr.

    发明人： Gordon Taylor Davis ,  Marco Heddes ,  Steven Kenneth Jenkins ,  Ross Boyd Leavens ,  Robert Brian Likovich, Jr.

    IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F12/14 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F9/52

    摘要： A generic method and apparatus for managing semaphores in a multi-threaded processing system has a storage area for each of the threads in the processing system. Each storage area includes a first part for storing at least one indicia for identifying at least one unique semaphore from a plurality of semaphores utilized by the multi-threaded processing system and a second part for storing an indicia for indicating a locked status for the stored semaphore. A thread requiring a semaphore sends a semaphore lock request to the semaphore manager which examines the contents of all of the storage areas to determine the status of the requested semaphore. If the requested semaphore is not locked, it is locked for the requesting thread by inserting the requested semaphore and locked status in the memory location assigned to the requesting thread.

    摘要翻译： 用于在多线程处理系统中管理信号量的通用方法和装置具有用于处理系统中的每个线程的存储区域。 每个存储区域包括第一部分，用于存储用于从多线程处理系统使用的多个信号量中识别至少一个唯一信号量的至少一个标记，以及用于存储用于指示所存储的信号量的锁定状态的标记的第二部分 。 需要信号量的线程向信号量管理器发送信号锁定请求，该信号量管理器检查所有存储区域的内容，以确定所请求的信号量的状态。 如果请求的信号量未被锁定，则通过将请求的信号量和锁定状态插入到分配给请求线程的存储器位置中来锁定请求线程。

    Network processor with single interface supporting tree search engine and CAM
    29.
    发明授权
    Network processor with single interface supporting tree search engine and CAM 失效
    具有单界面支持树搜索引擎和CAM的网络处理器

    公开(公告)号：US07167471B2

    公开(公告)日：2007-01-23

    申请号：US09940758

    申请日：2001-08-28

    申请人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    发明人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    IPC分类号： H04L12/56

    CPC分类号： H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

    摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

    摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。