公开(公告)号：US10103197B1

公开(公告)日：2018-10-16

申请号：US15650203

申请日：2017-07-14

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel ,  Sarin A. Deshpande

IPC: H01L29/82 ,  H01L43/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US10079339B2

公开(公告)日：2018-09-18

申请号：US15727905

申请日：2017-10-09

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Kerry Joseph Nagel ,  Chaitanya Mudivarthi ,  Sanjeev Aggarwal

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

公开(公告)号：US09793470B2

公开(公告)日：2017-10-17

申请号：US15013950

申请日：2016-02-02

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Kerry Joseph Nagel ,  Chaitanya Mudivarthi ,  Sanjeev Aggarwal

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching (i) the first encapsulation layer which is disposed over the exposed surface of the dielectric layer and (ii) re-deposited material disposed on the dielectric layer, wherein, thereafter a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region. The method further includes depositing a second encapsulation layer: (i) on the first encapsulation layer disposed on the sidewalls of the second magnetic region and (ii) over the exposed surface of the dielectric layer; and etching the remaining layers of the stack/structure (via one or more etch processes).

公开(公告)号：US09595665B2

公开(公告)日：2017-03-14

申请号：US15147682

申请日：2016-05-05

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel ,  Chaitanya Mudivarthi ,  Nicholas Rizzo ,  Jason Allen Janesky

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.

Abstract translation: 在形成用于磁阻器件的顶部电极时，使用非反应性剥离工艺剥离用于图案化电极的光致抗蚀剂。 这种非反应性汽提方法使用水蒸汽或一些其它非氧化气体，其也钝化了磁阻装置的暴露部分。 在这种磁阻器件中，包括非反应性间隔层，其有助于防止磁阻器件中的层之间的扩散，其中间隔层的非反应特性防止可能干扰磁阻的下部的精确形成的侧壁粗糙度 设备。

公开(公告)号：US09412786B1

公开(公告)日：2016-08-09

申请号：US14872708

申请日：2015-10-01

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel ,  Sarin A. Deshpande

IPC: H01L29/82 ,  H01L43/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L23/522

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

Abstract translation: 提出了磁阻器件结构和制造方法，其有助于将与将这些器件形成相关联的工艺步骤集成到用于周围逻辑/电路的标准工艺流程中。 在一些实施例中，磁阻器件结构被设计成使得器件能够安装在与单个金属层和单层层间电介质材料相关联的集成电路的垂直尺寸内。 集成用于磁阻器件的处理可以包括使用与在集成电路上的周围电路中使用的相同的标准层间绝缘材料，以及使用标准通孔来互连到磁阻器件的至少一个电极。

公开(公告)号：US09306157B2

公开(公告)日：2016-04-05

申请号：US14845697

申请日：2015-09-04

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Sanjeev Aggarwal

IPC: B44C1/22 ,  H01L43/12

CPC classification number: H01L43/12 ,  G11B5/84 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive-based device using a plurality of hard masks. The magnetoresistive-based device includes magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer. In one embodiment, the method may include removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively, and removing the tunnel barrier layer and the second magnetic materials layer unprotected by a second hard mask to form a tunnel barrier and second magnetic materials, and the second electrically conductive layer unprotected by the second hard mask to form, and a second electrode.

Abstract translation: 使用多个硬掩模制造基于磁阻的装置的方法。 基于磁阻的器件包括在第一导电层和第二导电层之间形成的磁性材料层，所述磁性材料层包括在第一磁性材料层和第二磁性材料层之间形成的隧道势垒层。 在一个实施例中，该方法可以包括移除未被第一硬掩模保护的第一导电层和第一磁性材料层，以分别形成第一电极和第一磁性材料，并且去除隧道势垒层和第二磁性层 材料层不被第二硬掩模保护以形成隧道势垒和第二磁性材料，以及由第二硬掩模未被保护以形成的第二导电层和第二电极。

公开(公告)号：US20150236250A1

公开(公告)日：2015-08-20

申请号：US14492768

申请日：2014-09-22

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/12

Abstract: A two-step etching process is used to form the top electrode for a magnetoresistive device. The etching chemistries are different for each of the two etching steps. The first chemistry used to etch the top portion of the electrode is more selective with respect to the conductive material of the top electrode, thereby reducing unwanted erosion of the photoresist and hard mask layers. The second chemistry is less corrosive than the first chemistry and does not damage the layers underlying the top electrode, such as those included in the magnetic tunnel junction.

Abstract translation: 使用两步蚀刻工艺来形成用于磁阻器件的顶部电极。 蚀刻化学品对于两个蚀刻步骤中的每一个都是不同的。 用于蚀刻电极顶部的第一化学品相对于顶部电极的导电材料更具选择性，从而减少光致抗蚀剂和硬掩模层的不必要的侵蚀。 第二种化学物质比第一种化学物质具有更少的腐蚀性，并且不会破坏顶部电极下面的层，例如包含在磁性隧道结中的层。

公开(公告)号：US20150236248A1

公开(公告)日：2015-08-20

申请号：US14296181

申请日：2014-06-04

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel ,  Nicholas Rizzo ,  Jason Allen Janesky

IPC: H01L43/12

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A two-step etching process is used to form the top electrode for a magnetoresistive device. The level of isotropy is different for each of the two etching steps, thereby providing advantages associated with isotropic etching as well as more anisotropic etching. The level of isotropy is controlled by varying power and pressure during plasma etching operations.

Abstract translation: 使用两步蚀刻工艺来形成用于磁阻器件的顶部电极。 各向同性的水平对于两个蚀刻步骤中的每一个都是不同的，从而提供与各向同性蚀刻相关的优点以及更多的各向异性蚀刻。 在等离子体蚀刻操作期间通过变化的功率和压力来控制各向同性的水平。

公开(公告)号：US20140315329A1

公开(公告)日：2014-10-23

申请号：US14264520

申请日：2014-04-29

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Sanjeev Aggarwal

IPC: H01L43/12

CPC classification number: H01L43/12 ,  G11B5/84 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode.

Abstract translation: 一种制造具有在第一导电层和第二导电层之间形成的磁性材料层的基于磁阻的器件的方法，所述磁性材料层包括在第一磁性材料层和第二磁性材料层之间形成的隧道势垒层， 包括去除未被第一硬掩模保护的第一导电层和第一磁性材料层，分别形成第一电极和第一磁性材料; 以及去除不受第二硬掩模保护的隧道势垒层，第二磁性材料层和第二导电层，以形成隧道势垒，第二磁性材料和第二电极。

公开(公告)号：US11778919B2

公开(公告)日：2023-10-03

申请号：US17510818

申请日：2021-10-26

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Kerry Joseph Nagel ,  Chaitanya Mudivarthi ,  Sanjeev Aggarwal

IPC: H10N50/01 ,  H10N50/10

CPC classification number: H10N50/01 ,  H10N50/10

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.