Method and apparatus for network table lookups
    21.
    发明申请
    Method and apparatus for network table lookups 审中-公开
    网络表查找的方法和装置

    公开(公告)号:US20130111122A1

    公开(公告)日:2013-05-02

    申请号:US13285728

    申请日:2011-10-31

    IPC分类号: G06F12/00 G06F12/06

    CPC分类号: G06F13/1647 G06F13/1684

    摘要: An apparatus comprising a plurality of memory components each comprising a plurality of memory banks, a memory controller coupled to the memory components and configured to control and select a one of the plurality of memory components for a memory operation, a plurality of address/command buses coupled to the plurality of memory components and the memory controller comprising at least one shared address/command bus between at least some of the plurality of memory components, and a plurality of data buses coupled to the memory components and the memory controller comprising at least one data bus between at least some of the memory components, wherein the memory controller uses a memory interleaving and bank arbitration scheme in a time-division multiplexing (TDM) fashion to access the plurality of memory components and the memory banks.

    摘要翻译: 一种装置,包括多个存储器组件,每个存储器组件包括多个存储器组,存储器控制器,耦合到存储器组件并被配置为控制和选择用于存储器操作的多个存储器组件中的一个,多个地址/命令总线 耦合到所述多个存储器组件,并且所述存储器控制器包括在所述多个存储器组件中的至少一些存储器组件之间的至少一个共享地址/命令总线以及耦合到所述存储器组件的多个数据总线以及包括至少一个 在至少一些存储器组件之间的数据总线,其中存储器控制器以时分复用(TDM)方式使用存储器交错和存储体仲裁方案来访问多个存储器组件和存储体。

    Large sized silicon interposers overcoming the reticle area limitations
    22.
    发明授权
    Large sized silicon interposers overcoming the reticle area limitations 有权
    大尺寸硅插入器克服了掩模版面积的局限性

    公开(公告)号:US08519543B1

    公开(公告)日:2013-08-27

    申请号:US13551466

    申请日:2012-07-17

    IPC分类号: H01L23/48

    摘要: A multi-die integrated circuit assembly includes an interposer substrate larger than the typical reticle size used in fabricating the “active area” in which the through-silicon vias (TSVs) and interconnect conductors are formed in the interposer. At the same time, each of the dies has its external power/ground and I/O signal line connections concentrated into a smaller area of the die. The dies are disposed or mounted on the interposer such that these smaller areas (with the power/ground/IO connections) overlap with the active area of the interposer. In this configuration, a plurality of dies having a combined area substantially greater than the active area of the interposer can be mounted on the interposer (and take advantage of the active area for interconnections).

    摘要翻译: 多模集成电路组件包括大于在制造其中在插入器中形成穿硅通孔(TSV)和互连导体的“有源区”中使用的典型标线尺寸的插入器基板。 同时,每个管芯都有其外部电源/接地和I / O信号线连接集中在芯片的较小区域。 模具设置或安装在插入器上,使得这些较小的区域(具有电源/接地/ IO连接)与插入器的有效区域重叠。 在该配置中,可以将具有基本上大于插入器的有效面积的组合面积的多个管芯安装在插入器上(并且利用有源区域进行互连)。

    Hardware-Based Dynamic Load Balancing That Avoids Flow Packet Reordering Statistically
    23.
    发明申请
    Hardware-Based Dynamic Load Balancing That Avoids Flow Packet Reordering Statistically 有权
    基于硬件的动态负载平衡,使流数据包重新排序统计

    公开(公告)号:US20130114414A1

    公开(公告)日:2013-05-09

    申请号:US13291198

    申请日:2011-11-08

    申请人: Haoyu Song

    发明人: Haoyu Song

    IPC分类号: H04L12/26 H04L12/56

    CPC分类号: H04L47/34 H04L47/125

    摘要: A network component comprising a hash generator configured to generate a first hash value using a first hash function and a packet, and generate a second hash value using a second hash function and the packet, a memory comprising a first hash table related to the first hash function and a second hash table related to the second hash function, the first and second hash tables comprising one or more entries, the one or more entries comprising a signature, a timestamp, and a path identification, a comparator configured to compare the first hash value and the second hash value with the one or more entries, and a forwarding decision module configured to forward the packet on a selected path.

    摘要翻译: 一种网络组件,包括哈希发生器,其被配置为使用第一散列函数和分组生成第一散列值,并且使用第二散列函数和所述分组生成第二散列值,所述存储器包括与所述第一散列函数相关的第一散列表 功能和与第二散列函数相关的第二散列表,所述第一和第二散列表包括一个或多个条目,所述一个或多个条目包括签名,时间戳和路径标识,比较器,被配置为比较第一散列 值和所述第二散列值与所述一个或多个条目相关联,以及转发决定模块,被配置为在所选择的路径上转发所述分组。

    Decoupled and Concurrent Packet Processing and Packet Buffering for Load-Balancing Router Architecture
    24.
    发明申请
    Decoupled and Concurrent Packet Processing and Packet Buffering for Load-Balancing Router Architecture 有权
    用于负载平衡路由器架构的解耦和并发数据包处理和数据包缓冲

    公开(公告)号:US20130114413A1

    公开(公告)日:2013-05-09

    申请号:US13291195

    申请日:2011-11-08

    IPC分类号: H04L12/26

    摘要: A network component comprising a traffic manager (TM) configured to assign a unique identifier (ID) to a received packet, a splitter module configured to separate a header and a payload of the received packet, the splitter module further configured to attach the unique ID to each of the header and the payload, and a merger module configured to assemble an outgoing packet using the header and the payload.

    摘要翻译: 一种网络组件,包括被配置为向所接收的分组分配唯一标识符(ID)的业务管理器(TM),被配置为分离所接收分组的报头和有效载荷的分离器模块,所述分组模块还被配置为附加所述唯一ID 到所述报头和所述有效载荷中的每一个,以及被配置为使用所述报头和所述有效载荷来组合输出分组的合并模块。

    Hardware-based dynamic load balancing that avoids flow packet reordering statistically
    25.
    发明授权
    Hardware-based dynamic load balancing that avoids flow packet reordering statistically 有权
    基于硬件的动态负载平衡,可以统计地避免流分组重排序

    公开(公告)号:US08976647B2

    公开(公告)日:2015-03-10

    申请号:US13291198

    申请日:2011-11-08

    申请人: Haoyu Song

    发明人: Haoyu Song

    CPC分类号: H04L47/34 H04L47/125

    摘要: A network component comprising a hash generator configured to generate a first hash value using a first hash function and a packet, and generate a second hash value using a second hash function and the packet, a memory comprising a first hash table related to the first hash function and a second hash table related to the second hash function, the first and second hash tables comprising one or more entries, the one or more entries comprising a signature, a timestamp, and a path identification, a comparator configured to compare the first hash value and the second hash value with the one or more entries, and a forwarding decision module configured to forward the packet on a selected path.

    摘要翻译: 一种网络组件,包括哈希发生器,其被配置为使用第一散列函数和分组生成第一散列值,并且使用第二散列函数和所述分组生成第二散列值,所述存储器包括与所述第一散列函数相关的第一散列表 功能和与第二散列函数相关的第二散列表,所述第一和第二散列表包括一个或多个条目,所述一个或多个条目包括签名,时间戳和路径标识,比较器,被配置为比较第一散列 值和所述第二散列值与所述一个或多个条目相关联,以及转发决定模块,被配置为在所选择的路径上转发所述分组。

    Decoupled and concurrent packet processing and packet buffering for load-balancing router architecture
    26.
    发明授权
    Decoupled and concurrent packet processing and packet buffering for load-balancing router architecture 有权
    用于负载平衡路由器架构的去耦和并发数据包处理和数据包缓冲

    公开(公告)号:US09014003B2

    公开(公告)日:2015-04-21

    申请号:US13291195

    申请日:2011-11-08

    摘要: A network component comprising a traffic manager (TM) configured to assign a unique identifier (ID) to a received packet, a splitter module configured to separate a header and a payload of the received packet, the splitter module further configured to attach the unique ID to each of the header and the payload, and a merger module configured to assemble an outgoing packet using the header and the payload.

    摘要翻译: 一种网络组件,包括被配置为向所接收的分组分配唯一标识符(ID)的业务管理器(TM),被配置为分离所接收分组的报头和有效载荷的分离器模块,所述分组模块还被配置为附加所述唯一ID 到所述报头和所述有效载荷中的每一个,以及被配置为使用所述报头和所述有效载荷来组合输出分组的合并模块。