公开(公告)号：US20070189103A1

公开(公告)日：2007-08-16

申请号：US11355802

申请日：2006-02-16

申请人： James Johnson ,  Feng Lin ,  Brent Keeth

发明人： James Johnson ,  Feng Lin ,  Brent Keeth

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/50 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in transmission of the internal Write Valid signal and system clock distribution to the deserializers in the data path portion of the write path, which is otherwise controlled by the intermittently asserted write strobe signal. With the input distribution delay of the system clock (Clk) and the write strobe (WS) matched by design, the distributed system clock and Write Valid signal are synchronized to the WS distribution path by means of the DLL delay with reference to the system clock input to the DLL. By backing the distribution delay out of system clock as sent to the deserializers, the write valid signal is effectively synchronized with the write strobe, with the effect that data will be passed out of the deserializer circuitry to the memory array on time and consistent with the programmed write latency.

摘要翻译： 公开了一种用于在SDRAM中改进写延迟跟踪的方法和电路。 在一个实施例中，在写入路径的命令部分中使用延迟锁定环，并且接收系统时钟作为其参考输入。 DLL包括建模延迟，其将内部写入有效信号的传输延迟和系统时钟分布建模到写入路径的数据路径部分中的解串行器，否则由间歇性断言的写入选通信号控制。 随着系统时钟（Clk）的输入分配延迟和设计匹配的写选通（WS），分布式系统时钟和写有效信号通过参考系统时钟的DLL延迟与WS分配路径同步 输入到DLL。 通过将分发延迟从发送到解串器的系统时钟中提取出来，写入有效信号与写入选通有效地同步，其影响是数据将及时从解串器电路传送到存储器阵列，并与 编程写延迟。

公开(公告)号：US07221201B2

公开(公告)日：2007-05-22

申请号：US10915774

申请日：2004-08-11

申请人： Feng Lin ,  Brent Keeth

发明人： Feng Lin ,  Brent Keeth

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/0814

摘要： A method and apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.

摘要翻译： 一种用于同步信号的方法和装置。 对于诸如存储设备的设备，实现同步设备来同步信号，可以实现具有耦合到锁相环路的延迟锁定环路的同步设备。 执行延迟锁定环路以测量参考信号的周期并将周期镜像成第二延迟线，使得可以生成具有近似等于参考时钟的频率的频率的经调整的参考信号。 调整的参考信号被传送到振荡器，使得振荡器以与参考时钟信号大致相同的频率开始振荡，以提供快速锁定同步装置。

公开(公告)号：US20060202726A1

公开(公告)日：2006-09-14

申请号：US11388226

申请日：2006-03-23

申请人： Feng Lin ,  Brent Keeth

发明人： Feng Lin ,  Brent Keeth

IPC分类号： H03L7/00

CPC分类号： H03L7/10 ,  H03L7/0814

摘要： An apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.

摘要翻译： 一种用于同步信号的装置。 对于诸如存储设备的设备，实现同步设备来同步信号，可以实现具有耦合到锁相环路的延迟锁定环路的同步设备。 执行延迟锁定环路以测量参考信号的周期并将周期镜像成第二延迟线，使得可以生成具有近似等于参考时钟的频率的频率的经调整的参考信号。 调整的参考信号被传送到振荡器，使得振荡器以与参考时钟信号大致相同的频率开始振荡，以提供快速锁定同步装置。

公开(公告)号：US20060033542A1

公开(公告)日：2006-02-16

申请号：US10915774

申请日：2004-08-11

申请人： Feng Lin ,  Brent Keeth

发明人： Feng Lin ,  Brent Keeth

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/0814

摘要： A method and apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.

摘要翻译： 一种用于同步信号的方法和装置。 对于诸如存储设备的设备，实现同步设备来同步信号，可以实现具有耦合到锁相环路的延迟锁定环路的同步设备。 执行延迟锁定环路以测量参考信号的周期并将周期镜像成第二延迟线，使得可以生成具有近似等于参考时钟的频率的频率的经调整的参考信号。 调整的参考信号被传送到振荡器，使得振荡器以与参考时钟信号大致相同的频率开始振荡，以提供快速锁定同步装置。

公开(公告)号：US07129738B2

公开(公告)日：2006-10-31

申请号：US10379006

申请日：2003-03-04

申请人： Feng Lin ,  Brian Johnson

发明人： Feng Lin ,  Brian Johnson

IPC分类号： H03K19/003

CPC分类号： H03K19/0005

摘要： The present invention provides a method and apparatus is provided for calibrating a driver impedance in an integrated circuit device. The method includes providing a signal from a synchronous circuit that is indicative of an impedance mismatch between a driver circuit and a load. The method also includes selecting one of a plurality of impedances of the driver circuit to reduce the impedance mismatch in response to the signal.

摘要翻译： 本发明提供了一种用于校准集成电路器件中的驱动器阻抗的方法和装置。 该方法包括提供来自指示驱动器电路和负载之间的阻抗失配的来自同步电路的信号。 该方法还包括选择驱动器电路的多个阻抗中的一个以减少响应于该信号的阻抗失配。

公开(公告)号：US06839301B2

公开(公告)日：2005-01-04

申请号：US10425069

申请日：2003-04-28

申请人： Feng Lin ,  J. Brian Johnson

发明人： Feng Lin ,  J. Brian Johnson

IPC分类号： G11C7/22 ,  G11C29/02 ,  G11C8/00

CPC分类号： G11C29/12015 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the test signal into the forward delay path and measures the time of traversal of the test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.

摘要翻译： 描述了延迟锁定环路，信号锁定方法和装置以及包含延迟锁定环路的系统。 延迟锁定环包括正向延迟路径，反馈延迟路径，相位检测器和定时器电路。 前向延迟路径交替耦合到外部时钟信号和内部测试信号。 相位检测器根据反馈信号和外部时钟信号的相位差调整延迟线。 定时器电路将测试信号切换到正向延迟路径，并测量在前向延迟路径和反馈延迟路径周围的测试信号遍历时间，并产生用于配置相位检测器更新周期的时间常数。 此后，相位检测器能够以更高的速率稳定。

公开(公告)号：US07812593B2

公开(公告)日：2010-10-12

申请号：US12202685

申请日：2008-09-02

申请人： Feng Lin ,  J. Brian Johnson

发明人： Feng Lin ,  J. Brian Johnson

IPC分类号： G01R17/16

CPC分类号： G11C29/12015 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： Delay-locked loops, signal locking methods and devices incorporating delay-locked loops are described. A delay-locked loop includes a forward loop path, a feedback loop path, and a phase detector. A test clock signal is temporarily switched to traverse the forward loop path and the feedback loop path. The phase detector is coupled to both the forward and feedback loop path circuits and is configured to periodically adjust responsive to a calculated loop delay of the test clock signal. The phase detector is thereafter able to stabilize at an improved rate.

摘要翻译： 描述了延迟锁定环路，信号锁定方法和包含延迟锁定环路的设备。 延迟锁定环路包括正向环路径，反馈环路径和相位检测器。 临时切换测试时钟信号以遍历正向环路径和反馈环路径。 相位检测器耦合到正向和反馈环路径电路两者，并且被配置为响应于所计算的测试时钟信号的环路延迟而周期性地调整。 此后，相位检测器能够以更高的速率稳定。

公开(公告)号：US07420361B2

公开(公告)日：2008-09-02

申请号：US11519556

申请日：2006-09-12

申请人： Feng Lin ,  J. Brian Johnson

发明人： Feng Lin ,  J. Brian Johnson

IPC分类号： G01R13/02

CPC分类号： G11C29/12015 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： Delay-locked loops, signal locking methods and devices and systems incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the internal test signal into the forward delay path and measures the time of traversal of the internal test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.

摘要翻译： 描述了延迟锁定环路，信号锁定方法以及包含延迟锁定环路的设备和系统。 延迟锁定环包括正向延迟路径，反馈延迟路径，相位检测器和定时器电路。 前向延迟路径交替耦合到外部时钟信号和内部测试信号。 相位检测器根据反馈信号和外部时钟信号的相位差调整延迟线。 定时器电路将内部测试信号切换到正向延迟路径，并测量在正向延迟路径和反馈延迟路径周围的内部测试信号的遍历时间，并产生用于配置相位检测器更新周期的时间常数。 此后，相位检测器能够以更高的速率稳定。

公开(公告)号：US07436202B2

公开(公告)日：2008-10-14

申请号：US11523491

申请日：2006-09-19

申请人： Feng Lin ,  Brian Johnson

发明人： Feng Lin ,  Brian Johnson

IPC分类号： H03K19/003

CPC分类号： H03K19/0005

摘要： The present invention provides a method and apparatus is provided for calibrating a driver impedance in an integrated circuit device. The method includes providing a signal from a synchronous circuit that is indicative of an impedance mismatch between a driver circuit and a load. The method also includes selecting one of a plurality of impedances of the driver circuit to reduce the impedance mismatch in response to the signal.

摘要翻译： 本发明提供了一种用于校准集成电路器件中的驱动器阻抗的方法和装置。 该方法包括提供来自指示驱动器电路和负载之间的阻抗失配的来自同步电路的信号。 该方法还包括选择驱动器电路的多个阻抗中的一个以减少响应于该信号的阻抗失配。

公开(公告)号：US20090002041A1

公开(公告)日：2009-01-01

申请号：US12202685

申请日：2008-09-02

申请人： Feng Lin ,  J. Brian Johnson

发明人： Feng Lin ,  J. Brian Johnson

IPC分类号： H03L7/06

CPC分类号： G11C29/12015 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： Delay-locked loops, signal locking methods and devices and systems incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the internal test signal into the forward delay path and measures the time of traversal of the internal test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.

摘要翻译： 描述了延迟锁定环路，信号锁定方法以及包含延迟锁定环路的设备和系统。 延迟锁定环包括正向延迟路径，反馈延迟路径，相位检测器和定时器电路。 前向延迟路径交替耦合到外部时钟信号和内部测试信号。 相位检测器根据反馈信号和外部时钟信号的相位差调整延迟线。 定时器电路将内部测试信号切换到正向延迟路径，并测量在正向延迟路径和反馈延迟路径周围的内部测试信号的遍历时间，并产生用于配置相位检测器更新周期的时间常数。 此后，相位检测器能够以更高的速率稳定。